1f46a221bSXiaojian Du /*
2f46a221bSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc.
3f46a221bSXiaojian Du *
4f46a221bSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a
5f46a221bSXiaojian Du * copy of this software and associated documentation files (the "Software"),
6f46a221bSXiaojian Du * to deal in the Software without restriction, including without limitation
7f46a221bSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f46a221bSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the
9f46a221bSXiaojian Du * Software is furnished to do so, subject to the following conditions:
10f46a221bSXiaojian Du *
11f46a221bSXiaojian Du * The above copyright notice and this permission notice shall be included in
12f46a221bSXiaojian Du * all copies or substantial portions of the Software.
13f46a221bSXiaojian Du *
14f46a221bSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f46a221bSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f46a221bSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f46a221bSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f46a221bSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f46a221bSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f46a221bSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE.
21f46a221bSXiaojian Du *
22f46a221bSXiaojian Du */
23f46a221bSXiaojian Du
24f46a221bSXiaojian Du #define SWSMU_CODE_LAYER_L2
25f46a221bSXiaojian Du
26f46a221bSXiaojian Du #include "amdgpu.h"
27f46a221bSXiaojian Du #include "amdgpu_smu.h"
28f46a221bSXiaojian Du #include "smu_v11_0.h"
29f46a221bSXiaojian Du #include "smu11_driver_if_vangogh.h"
30f46a221bSXiaojian Du #include "vangogh_ppt.h"
31f46a221bSXiaojian Du #include "smu_v11_5_ppsmc.h"
32f46a221bSXiaojian Du #include "smu_v11_5_pmfw.h"
33f46a221bSXiaojian Du #include "smu_cmn.h"
34eefdf047SJinzhou Su #include "soc15_common.h"
35eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_offset.h"
36eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37517cb957SHuang Rui #include <asm/processor.h>
38f46a221bSXiaojian Du
39f46a221bSXiaojian Du /*
40f46a221bSXiaojian Du * DO NOT use these for err/warn/info/debug messages.
41f46a221bSXiaojian Du * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42f46a221bSXiaojian Du * They are more MGPU friendly.
43f46a221bSXiaojian Du */
44f46a221bSXiaojian Du #undef pr_err
45f46a221bSXiaojian Du #undef pr_warn
46f46a221bSXiaojian Du #undef pr_info
47f46a221bSXiaojian Du #undef pr_debug
48f46a221bSXiaojian Du
4943195162SAndré Almeida // Registers related to GFXOFF
5043195162SAndré Almeida // addressBlock: smuio_smuio_SmuSmuioDec
5143195162SAndré Almeida // base address: 0x5a000
5243195162SAndré Almeida #define mmSMUIO_GFX_MISC_CNTL 0x00c5
5343195162SAndré Almeida #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
5443195162SAndré Almeida
5543195162SAndré Almeida //SMUIO_GFX_MISC_CNTL
5643195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
5743195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
5843195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
5943195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
6043195162SAndré Almeida
61f46a221bSXiaojian Du #define FEATURE_MASK(feature) (1ULL << feature)
62f46a221bSXiaojian Du #define SMC_DPM_FEATURE ( \
63f46a221bSXiaojian Du FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64f46a221bSXiaojian Du FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
65f46a221bSXiaojian Du FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
66f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
67f46a221bSXiaojian Du FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
68f46a221bSXiaojian Du FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
69f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
70f46a221bSXiaojian Du FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71271ab489SXiaojian Du FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72f46a221bSXiaojian Du
73f46a221bSXiaojian Du static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74271ab489SXiaojian Du MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
75271ab489SXiaojian Du MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
76271ab489SXiaojian Du MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
77271ab489SXiaojian Du MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
78b58ce1feSJinzhou Su MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
79b58ce1feSJinzhou Su MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
80271ab489SXiaojian Du MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
81271ab489SXiaojian Du MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
82271ab489SXiaojian Du MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
83271ab489SXiaojian Du MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
84a0f55287SXiaomeng Hou MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
85271ab489SXiaojian Du MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
86271ab489SXiaojian Du MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
87271ab489SXiaojian Du MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
88271ab489SXiaojian Du MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
89271ab489SXiaojian Du MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
90271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
91271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
92271ab489SXiaojian Du MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93271ab489SXiaojian Du MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94271ab489SXiaojian Du MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
95271ab489SXiaojian Du MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
96271ab489SXiaojian Du MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
97271ab489SXiaojian Du MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
98271ab489SXiaojian Du MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
99271ab489SXiaojian Du MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
100271ab489SXiaojian Du MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
101271ab489SXiaojian Du MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
102271ab489SXiaojian Du MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
103271ab489SXiaojian Du MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
104271ab489SXiaojian Du MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
105271ab489SXiaojian Du MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
106271ab489SXiaojian Du MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
107271ab489SXiaojian Du MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
108271ab489SXiaojian Du MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
109271ab489SXiaojian Du MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110271ab489SXiaojian Du MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
111271ab489SXiaojian Du MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
112271ab489SXiaojian Du MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
113271ab489SXiaojian Du MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
114271ab489SXiaojian Du MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
115271ab489SXiaojian Du MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
116271ab489SXiaojian Du MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
117271ab489SXiaojian Du MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
118271ab489SXiaojian Du MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
119271ab489SXiaojian Du MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
120271ab489SXiaojian Du MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
121271ab489SXiaojian Du MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
122271ab489SXiaojian Du MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
123271ab489SXiaojian Du MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
124271ab489SXiaojian Du MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
125271ab489SXiaojian Du MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
126271ab489SXiaojian Du MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
127271ab489SXiaojian Du MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
128271ab489SXiaojian Du MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
129271ab489SXiaojian Du MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
130271ab489SXiaojian Du MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
131271ab489SXiaojian Du MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
132271ab489SXiaojian Du MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
133271ab489SXiaojian Du MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
134271ab489SXiaojian Du MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
135271ab489SXiaojian Du MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
136eefdf047SJinzhou Su MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
137ae07970aSXiaomeng Hou MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
138ae07970aSXiaomeng Hou MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
139ae07970aSXiaomeng Hou MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
140ae07970aSXiaomeng Hou MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
1411ed5a845SAndré Almeida MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
1421ed5a845SAndré Almeida MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
1431ed5a845SAndré Almeida MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
144f46a221bSXiaojian Du };
145f46a221bSXiaojian Du
146f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147f46a221bSXiaojian Du FEA_MAP(PPT),
148f46a221bSXiaojian Du FEA_MAP(TDC),
149f46a221bSXiaojian Du FEA_MAP(THERMAL),
150f46a221bSXiaojian Du FEA_MAP(DS_GFXCLK),
151f46a221bSXiaojian Du FEA_MAP(DS_SOCCLK),
152f46a221bSXiaojian Du FEA_MAP(DS_LCLK),
153f46a221bSXiaojian Du FEA_MAP(DS_FCLK),
154f46a221bSXiaojian Du FEA_MAP(DS_MP1CLK),
155f46a221bSXiaojian Du FEA_MAP(DS_MP0CLK),
156f46a221bSXiaojian Du FEA_MAP(ATHUB_PG),
157f46a221bSXiaojian Du FEA_MAP(CCLK_DPM),
158f46a221bSXiaojian Du FEA_MAP(FAN_CONTROLLER),
159f46a221bSXiaojian Du FEA_MAP(ULV),
160f46a221bSXiaojian Du FEA_MAP(VCN_DPM),
161f46a221bSXiaojian Du FEA_MAP(LCLK_DPM),
162f46a221bSXiaojian Du FEA_MAP(SHUBCLK_DPM),
163f46a221bSXiaojian Du FEA_MAP(DCFCLK_DPM),
164f46a221bSXiaojian Du FEA_MAP(DS_DCFCLK),
165f46a221bSXiaojian Du FEA_MAP(S0I2),
166f46a221bSXiaojian Du FEA_MAP(SMU_LOW_POWER),
167f46a221bSXiaojian Du FEA_MAP(GFX_DEM),
168f46a221bSXiaojian Du FEA_MAP(PSI),
169f46a221bSXiaojian Du FEA_MAP(PROCHOT),
170f46a221bSXiaojian Du FEA_MAP(CPUOFF),
171f46a221bSXiaojian Du FEA_MAP(STAPM),
172f46a221bSXiaojian Du FEA_MAP(S0I3),
173f46a221bSXiaojian Du FEA_MAP(DF_CSTATES),
174f46a221bSXiaojian Du FEA_MAP(PERF_LIMIT),
175f46a221bSXiaojian Du FEA_MAP(CORE_DLDO),
176f46a221bSXiaojian Du FEA_MAP(RSMU_LOW_POWER),
177f46a221bSXiaojian Du FEA_MAP(SMN_LOW_POWER),
178f46a221bSXiaojian Du FEA_MAP(THM_LOW_POWER),
179f46a221bSXiaojian Du FEA_MAP(SMUIO_LOW_POWER),
180f46a221bSXiaojian Du FEA_MAP(MP1_LOW_POWER),
181f46a221bSXiaojian Du FEA_MAP(DS_VCN),
182f46a221bSXiaojian Du FEA_MAP(CPPC),
183f46a221bSXiaojian Du FEA_MAP(OS_CSTATES),
184f46a221bSXiaojian Du FEA_MAP(ISP_DPM),
185f46a221bSXiaojian Du FEA_MAP(A55_DPM),
186f46a221bSXiaojian Du FEA_MAP(CVIP_DSP_DPM),
187f46a221bSXiaojian Du FEA_MAP(MSMU_LOW_POWER),
18854800b58SXiaojian Du FEA_MAP_REVERSE(SOCCLK),
18954800b58SXiaojian Du FEA_MAP_REVERSE(FCLK),
19054800b58SXiaojian Du FEA_MAP_HALF_REVERSE(GFX),
191f46a221bSXiaojian Du };
192f46a221bSXiaojian Du
193f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194f46a221bSXiaojian Du TAB_MAP_VALID(WATERMARKS),
195f46a221bSXiaojian Du TAB_MAP_VALID(SMU_METRICS),
196f46a221bSXiaojian Du TAB_MAP_VALID(CUSTOM_DPM),
197f46a221bSXiaojian Du TAB_MAP_VALID(DPMCLOCKS),
198f46a221bSXiaojian Du };
199f46a221bSXiaojian Du
200f727ebebSXiaojian Du static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
203f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
204f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
205f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
206dc622367SPerry Yuan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
207dc622367SPerry Yuan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
208f727ebebSXiaojian Du };
209f727ebebSXiaojian Du
2107cab3cffSGraham Sider static const uint8_t vangogh_throttler_map[] = {
2117cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
2127cab3cffSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
2137cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
2147cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
2157cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
2167cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
2177cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
2187cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
2197cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
2207cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
2217cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
2227cab3cffSGraham Sider };
2237cab3cffSGraham Sider
vangogh_tables_init(struct smu_context * smu)224f46a221bSXiaojian Du static int vangogh_tables_init(struct smu_context *smu)
225f46a221bSXiaojian Du {
226f46a221bSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
227f46a221bSXiaojian Du struct smu_table *tables = smu_table->tables;
228f46a221bSXiaojian Du
229f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
230f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
231f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
232f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
234f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
236f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237908cebc9SLi Ma SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
238908cebc9SLi Ma PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
23986c8236eSXiaojian Du
240908cebc9SLi Ma smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
241f46a221bSXiaojian Du if (!smu_table->metrics_table)
242f46a221bSXiaojian Du goto err0_out;
243f46a221bSXiaojian Du smu_table->metrics_time = 0;
244f46a221bSXiaojian Du
245908cebc9SLi Ma smu_table->gpu_metrics_table_size = max(sizeof(struct gpu_metrics_v2_3), sizeof(struct gpu_metrics_v2_2));
246f46a221bSXiaojian Du smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
247f46a221bSXiaojian Du if (!smu_table->gpu_metrics_table)
248f46a221bSXiaojian Du goto err1_out;
249f46a221bSXiaojian Du
250f46a221bSXiaojian Du smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
251f46a221bSXiaojian Du if (!smu_table->watermarks_table)
252f46a221bSXiaojian Du goto err2_out;
253f46a221bSXiaojian Du
254c98ee897SXiaojian Du smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
255c98ee897SXiaojian Du if (!smu_table->clocks_table)
256c98ee897SXiaojian Du goto err3_out;
257c98ee897SXiaojian Du
258f46a221bSXiaojian Du return 0;
259f46a221bSXiaojian Du
260c98ee897SXiaojian Du err3_out:
261a5467ebdSChristophe JAILLET kfree(smu_table->watermarks_table);
262f46a221bSXiaojian Du err2_out:
263f46a221bSXiaojian Du kfree(smu_table->gpu_metrics_table);
264f46a221bSXiaojian Du err1_out:
265f46a221bSXiaojian Du kfree(smu_table->metrics_table);
266f46a221bSXiaojian Du err0_out:
267f46a221bSXiaojian Du return -ENOMEM;
268f46a221bSXiaojian Du }
269f46a221bSXiaojian Du
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)27086c8236eSXiaojian Du static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
271271ab489SXiaojian Du MetricsMember_t member,
272271ab489SXiaojian Du uint32_t *value)
273271ab489SXiaojian Du {
274271ab489SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
27586c8236eSXiaojian Du SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
276271ab489SXiaojian Du int ret = 0;
277271ab489SXiaojian Du
278da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu,
279271ab489SXiaojian Du NULL,
280271ab489SXiaojian Du false);
281da11407fSEvan Quan if (ret)
282271ab489SXiaojian Du return ret;
283271ab489SXiaojian Du
284271ab489SXiaojian Du switch (member) {
285a99a5116SXiaojian Du case METRICS_CURR_GFXCLK:
286271ab489SXiaojian Du *value = metrics->GfxclkFrequency;
287271ab489SXiaojian Du break;
288271ab489SXiaojian Du case METRICS_AVERAGE_SOCCLK:
289271ab489SXiaojian Du *value = metrics->SocclkFrequency;
290271ab489SXiaojian Du break;
291f02c7336SXiaojian Du case METRICS_AVERAGE_VCLK:
292f02c7336SXiaojian Du *value = metrics->VclkFrequency;
293f02c7336SXiaojian Du break;
294f02c7336SXiaojian Du case METRICS_AVERAGE_DCLK:
295f02c7336SXiaojian Du *value = metrics->DclkFrequency;
296f02c7336SXiaojian Du break;
297a99a5116SXiaojian Du case METRICS_CURR_UCLK:
298271ab489SXiaojian Du *value = metrics->MemclkFrequency;
299271ab489SXiaojian Du break;
300271ab489SXiaojian Du case METRICS_AVERAGE_GFXACTIVITY:
301271ab489SXiaojian Du *value = metrics->GfxActivity / 100;
302271ab489SXiaojian Du break;
303271ab489SXiaojian Du case METRICS_AVERAGE_VCNACTIVITY:
3042a88f1b5SXiaojian Du *value = metrics->UvdActivity / 100;
305271ab489SXiaojian Du break;
306271ab489SXiaojian Du case METRICS_AVERAGE_SOCKETPOWER:
30723289a22SXiaojian Du *value = (metrics->CurrentSocketPower << 8) /
30823289a22SXiaojian Du 1000 ;
309271ab489SXiaojian Du break;
310271ab489SXiaojian Du case METRICS_TEMPERATURE_EDGE:
311271ab489SXiaojian Du *value = metrics->GfxTemperature / 100 *
312271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
313271ab489SXiaojian Du break;
314271ab489SXiaojian Du case METRICS_TEMPERATURE_HOTSPOT:
315271ab489SXiaojian Du *value = metrics->SocTemperature / 100 *
316271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
317271ab489SXiaojian Du break;
318271ab489SXiaojian Du case METRICS_THROTTLER_STATUS:
319271ab489SXiaojian Du *value = metrics->ThrottlerStatus;
320271ab489SXiaojian Du break;
3212139d12bSAlex Deucher case METRICS_VOLTAGE_VDDGFX:
3222139d12bSAlex Deucher *value = metrics->Voltage[2];
3232139d12bSAlex Deucher break;
3242139d12bSAlex Deucher case METRICS_VOLTAGE_VDDSOC:
3252139d12bSAlex Deucher *value = metrics->Voltage[1];
3262139d12bSAlex Deucher break;
327517cb957SHuang Rui case METRICS_AVERAGE_CPUCLK:
328517cb957SHuang Rui memcpy(value, &metrics->CoreFrequency[0],
3294aef0ebcSHuang Rui smu->cpu_core_num * sizeof(uint16_t));
330517cb957SHuang Rui break;
331271ab489SXiaojian Du default:
332271ab489SXiaojian Du *value = UINT_MAX;
333271ab489SXiaojian Du break;
334271ab489SXiaojian Du }
335271ab489SXiaojian Du
336271ab489SXiaojian Du return ret;
337271ab489SXiaojian Du }
338271ab489SXiaojian Du
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)33986c8236eSXiaojian Du static int vangogh_get_smu_metrics_data(struct smu_context *smu,
34086c8236eSXiaojian Du MetricsMember_t member,
34186c8236eSXiaojian Du uint32_t *value)
34286c8236eSXiaojian Du {
34386c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
34486c8236eSXiaojian Du SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
34586c8236eSXiaojian Du int ret = 0;
34686c8236eSXiaojian Du
347da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu,
34886c8236eSXiaojian Du NULL,
34986c8236eSXiaojian Du false);
350da11407fSEvan Quan if (ret)
35186c8236eSXiaojian Du return ret;
35286c8236eSXiaojian Du
35386c8236eSXiaojian Du switch (member) {
354a99a5116SXiaojian Du case METRICS_CURR_GFXCLK:
35586c8236eSXiaojian Du *value = metrics->Current.GfxclkFrequency;
35686c8236eSXiaojian Du break;
35786c8236eSXiaojian Du case METRICS_AVERAGE_SOCCLK:
35886c8236eSXiaojian Du *value = metrics->Current.SocclkFrequency;
35986c8236eSXiaojian Du break;
36086c8236eSXiaojian Du case METRICS_AVERAGE_VCLK:
36186c8236eSXiaojian Du *value = metrics->Current.VclkFrequency;
36286c8236eSXiaojian Du break;
36386c8236eSXiaojian Du case METRICS_AVERAGE_DCLK:
36486c8236eSXiaojian Du *value = metrics->Current.DclkFrequency;
36586c8236eSXiaojian Du break;
366a99a5116SXiaojian Du case METRICS_CURR_UCLK:
36786c8236eSXiaojian Du *value = metrics->Current.MemclkFrequency;
36886c8236eSXiaojian Du break;
36986c8236eSXiaojian Du case METRICS_AVERAGE_GFXACTIVITY:
37086c8236eSXiaojian Du *value = metrics->Current.GfxActivity;
37186c8236eSXiaojian Du break;
37286c8236eSXiaojian Du case METRICS_AVERAGE_VCNACTIVITY:
37386c8236eSXiaojian Du *value = metrics->Current.UvdActivity;
37486c8236eSXiaojian Du break;
37586c8236eSXiaojian Du case METRICS_AVERAGE_SOCKETPOWER:
37647f1724dSMario Limonciello *value = (metrics->Average.CurrentSocketPower << 8) /
37747f1724dSMario Limonciello 1000;
37847f1724dSMario Limonciello break;
37947f1724dSMario Limonciello case METRICS_CURR_SOCKETPOWER:
38086c8236eSXiaojian Du *value = (metrics->Current.CurrentSocketPower << 8) /
38186c8236eSXiaojian Du 1000;
38286c8236eSXiaojian Du break;
38386c8236eSXiaojian Du case METRICS_TEMPERATURE_EDGE:
38486c8236eSXiaojian Du *value = metrics->Current.GfxTemperature / 100 *
38586c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
38686c8236eSXiaojian Du break;
38786c8236eSXiaojian Du case METRICS_TEMPERATURE_HOTSPOT:
38886c8236eSXiaojian Du *value = metrics->Current.SocTemperature / 100 *
38986c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
39086c8236eSXiaojian Du break;
39186c8236eSXiaojian Du case METRICS_THROTTLER_STATUS:
39286c8236eSXiaojian Du *value = metrics->Current.ThrottlerStatus;
39386c8236eSXiaojian Du break;
39486c8236eSXiaojian Du case METRICS_VOLTAGE_VDDGFX:
39586c8236eSXiaojian Du *value = metrics->Current.Voltage[2];
39686c8236eSXiaojian Du break;
39786c8236eSXiaojian Du case METRICS_VOLTAGE_VDDSOC:
39886c8236eSXiaojian Du *value = metrics->Current.Voltage[1];
39986c8236eSXiaojian Du break;
40086c8236eSXiaojian Du case METRICS_AVERAGE_CPUCLK:
40186c8236eSXiaojian Du memcpy(value, &metrics->Current.CoreFrequency[0],
40286c8236eSXiaojian Du smu->cpu_core_num * sizeof(uint16_t));
40386c8236eSXiaojian Du break;
40486c8236eSXiaojian Du default:
40586c8236eSXiaojian Du *value = UINT_MAX;
40686c8236eSXiaojian Du break;
40786c8236eSXiaojian Du }
40886c8236eSXiaojian Du
40986c8236eSXiaojian Du return ret;
41086c8236eSXiaojian Du }
41186c8236eSXiaojian Du
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)41286c8236eSXiaojian Du static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
41386c8236eSXiaojian Du MetricsMember_t member,
41486c8236eSXiaojian Du uint32_t *value)
41586c8236eSXiaojian Du {
41686c8236eSXiaojian Du int ret = 0;
41786c8236eSXiaojian Du
418710d9caeSYifan Zhang if (smu->smc_fw_if_version < 0x3)
41986c8236eSXiaojian Du ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
42086c8236eSXiaojian Du else
42186c8236eSXiaojian Du ret = vangogh_get_smu_metrics_data(smu, member, value);
42286c8236eSXiaojian Du
42386c8236eSXiaojian Du return ret;
42486c8236eSXiaojian Du }
42586c8236eSXiaojian Du
vangogh_allocate_dpm_context(struct smu_context * smu)426f46a221bSXiaojian Du static int vangogh_allocate_dpm_context(struct smu_context *smu)
427f46a221bSXiaojian Du {
428f46a221bSXiaojian Du struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
429f46a221bSXiaojian Du
430f46a221bSXiaojian Du smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
431f46a221bSXiaojian Du GFP_KERNEL);
432f46a221bSXiaojian Du if (!smu_dpm->dpm_context)
433f46a221bSXiaojian Du return -ENOMEM;
434f46a221bSXiaojian Du
435f46a221bSXiaojian Du smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
436f46a221bSXiaojian Du
437f46a221bSXiaojian Du return 0;
438f46a221bSXiaojian Du }
439f46a221bSXiaojian Du
vangogh_init_smc_tables(struct smu_context * smu)440f46a221bSXiaojian Du static int vangogh_init_smc_tables(struct smu_context *smu)
441f46a221bSXiaojian Du {
442f46a221bSXiaojian Du int ret = 0;
443f46a221bSXiaojian Du
444f46a221bSXiaojian Du ret = vangogh_tables_init(smu);
445f46a221bSXiaojian Du if (ret)
446f46a221bSXiaojian Du return ret;
447f46a221bSXiaojian Du
448f46a221bSXiaojian Du ret = vangogh_allocate_dpm_context(smu);
449f46a221bSXiaojian Du if (ret)
450f46a221bSXiaojian Du return ret;
451f46a221bSXiaojian Du
4524aef0ebcSHuang Rui #ifdef CONFIG_X86
4534aef0ebcSHuang Rui /* AMD x86 APU only */
45489b0f15fSThomas Gleixner smu->cpu_core_num = topology_num_cores_per_package();
4554aef0ebcSHuang Rui #else
4564aef0ebcSHuang Rui smu->cpu_core_num = 4;
4574aef0ebcSHuang Rui #endif
4584aef0ebcSHuang Rui
459f46a221bSXiaojian Du return smu_v11_0_init_smc_tables(smu);
460f46a221bSXiaojian Du }
461f46a221bSXiaojian Du
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)462f46a221bSXiaojian Du static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
463f46a221bSXiaojian Du {
464f46a221bSXiaojian Du int ret = 0;
465f46a221bSXiaojian Du
466f46a221bSXiaojian Du if (enable) {
467f46a221bSXiaojian Du /* vcn dpm on is a prerequisite for vcn power gate messages */
468f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
469f46a221bSXiaojian Du if (ret)
470f46a221bSXiaojian Du return ret;
471f46a221bSXiaojian Du } else {
472f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
473f46a221bSXiaojian Du if (ret)
474f46a221bSXiaojian Du return ret;
475f46a221bSXiaojian Du }
476f46a221bSXiaojian Du
477f46a221bSXiaojian Du return ret;
478f46a221bSXiaojian Du }
479f46a221bSXiaojian Du
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)480f46a221bSXiaojian Du static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
481f46a221bSXiaojian Du {
482f46a221bSXiaojian Du int ret = 0;
483f46a221bSXiaojian Du
484f46a221bSXiaojian Du if (enable) {
485f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
486f46a221bSXiaojian Du if (ret)
487f46a221bSXiaojian Du return ret;
488f46a221bSXiaojian Du } else {
489f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
490f46a221bSXiaojian Du if (ret)
491f46a221bSXiaojian Du return ret;
492f46a221bSXiaojian Du }
493f46a221bSXiaojian Du
494f46a221bSXiaojian Du return ret;
495f46a221bSXiaojian Du }
496f46a221bSXiaojian Du
vangogh_is_dpm_running(struct smu_context * smu)497f46a221bSXiaojian Du static bool vangogh_is_dpm_running(struct smu_context *smu)
498f46a221bSXiaojian Du {
4991c0f0430SAlex Deucher struct amdgpu_device *adev = smu->adev;
500271ab489SXiaojian Du int ret = 0;
501271ab489SXiaojian Du uint64_t feature_enabled;
502f46a221bSXiaojian Du
5031c0f0430SAlex Deucher /* we need to re-init after suspend so return false */
5041c0f0430SAlex Deucher if (adev->in_suspend)
5051c0f0430SAlex Deucher return false;
5061c0f0430SAlex Deucher
5072d282665SEvan Quan ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
508271ab489SXiaojian Du
509271ab489SXiaojian Du if (ret)
510f46a221bSXiaojian Du return false;
511f46a221bSXiaojian Du
512271ab489SXiaojian Du return !!(feature_enabled & SMC_DPM_FEATURE);
513271ab489SXiaojian Du }
514271ab489SXiaojian Du
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)515ae7b32e7SXiaojian Du static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
516ae7b32e7SXiaojian Du uint32_t dpm_level, uint32_t *freq)
517ae7b32e7SXiaojian Du {
518ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
519ae7b32e7SXiaojian Du
520ae7b32e7SXiaojian Du if (!clk_table || clk_type >= SMU_CLK_COUNT)
521ae7b32e7SXiaojian Du return -EINVAL;
522ae7b32e7SXiaojian Du
523ae7b32e7SXiaojian Du switch (clk_type) {
524ae7b32e7SXiaojian Du case SMU_SOCCLK:
525ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
526ae7b32e7SXiaojian Du return -EINVAL;
527ae7b32e7SXiaojian Du *freq = clk_table->SocClocks[dpm_level];
528ae7b32e7SXiaojian Du break;
529f02c7336SXiaojian Du case SMU_VCLK:
530f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled)
531f02c7336SXiaojian Du return -EINVAL;
532f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].vclk;
533f02c7336SXiaojian Du break;
534f02c7336SXiaojian Du case SMU_DCLK:
535f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled)
536f02c7336SXiaojian Du return -EINVAL;
537f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].dclk;
538f02c7336SXiaojian Du break;
539ae7b32e7SXiaojian Du case SMU_UCLK:
540ae7b32e7SXiaojian Du case SMU_MCLK:
541ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled)
542ae7b32e7SXiaojian Du return -EINVAL;
543ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].memclk;
544ae7b32e7SXiaojian Du
545ae7b32e7SXiaojian Du break;
546ae7b32e7SXiaojian Du case SMU_FCLK:
547ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled)
548ae7b32e7SXiaojian Du return -EINVAL;
549ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].fclk;
550ae7b32e7SXiaojian Du break;
551ae7b32e7SXiaojian Du default:
552ae7b32e7SXiaojian Du return -EINVAL;
553ae7b32e7SXiaojian Du }
554ae7b32e7SXiaojian Du
555ae7b32e7SXiaojian Du return 0;
556ae7b32e7SXiaojian Du }
557ae7b32e7SXiaojian Du
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)55886c8236eSXiaojian Du static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
559c98ee897SXiaojian Du enum smu_clk_type clk_type, char *buf)
560c98ee897SXiaojian Du {
561ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
56286c8236eSXiaojian Du SmuMetrics_legacy_t metrics;
563d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
56463b9acdfSTim Huang int i, idx, size = 0, ret = 0;
565ae7b32e7SXiaojian Du uint32_t cur_value = 0, value = 0, count = 0;
566ae7b32e7SXiaojian Du bool cur_value_match_level = false;
567ae7b32e7SXiaojian Du
568ae7b32e7SXiaojian Du memset(&metrics, 0, sizeof(metrics));
569ae7b32e7SXiaojian Du
570ae7b32e7SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false);
571ae7b32e7SXiaojian Du if (ret)
572ae7b32e7SXiaojian Du return ret;
573c98ee897SXiaojian Du
5748f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size);
5758f48ba30SLang Yu
576c98ee897SXiaojian Du switch (clk_type) {
577c98ee897SXiaojian Du case SMU_OD_SCLK:
578d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
5798f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
580fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
581c98ee897SXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
582fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
583c98ee897SXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
584c98ee897SXiaojian Du }
585c98ee897SXiaojian Du break;
5860d90d0ddSHuang Rui case SMU_OD_CCLK:
587d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
5888f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
589fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
5900d90d0ddSHuang Rui (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
591fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
5920d90d0ddSHuang Rui (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
5930d90d0ddSHuang Rui }
5940d90d0ddSHuang Rui break;
595c98ee897SXiaojian Du case SMU_OD_RANGE:
596d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
5978f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
598fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
599c98ee897SXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
600fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
6010d90d0ddSHuang Rui smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
602c98ee897SXiaojian Du }
603c98ee897SXiaojian Du break;
604ae7b32e7SXiaojian Du case SMU_SOCCLK:
605ae7b32e7SXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
606ae7b32e7SXiaojian Du count = clk_table->NumSocClkLevelsEnabled;
607ae7b32e7SXiaojian Du cur_value = metrics.SocclkFrequency;
608ae7b32e7SXiaojian Du break;
609f02c7336SXiaojian Du case SMU_VCLK:
610f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled;
611f02c7336SXiaojian Du cur_value = metrics.VclkFrequency;
612f02c7336SXiaojian Du break;
613f02c7336SXiaojian Du case SMU_DCLK:
614f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled;
615f02c7336SXiaojian Du cur_value = metrics.DclkFrequency;
616f02c7336SXiaojian Du break;
617ae7b32e7SXiaojian Du case SMU_MCLK:
618ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled;
619ae7b32e7SXiaojian Du cur_value = metrics.MemclkFrequency;
620ae7b32e7SXiaojian Du break;
621ae7b32e7SXiaojian Du case SMU_FCLK:
622ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled;
623ae7b32e7SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
624ae7b32e7SXiaojian Du if (ret)
625ae7b32e7SXiaojian Du return ret;
626ae7b32e7SXiaojian Du break;
627ae7b32e7SXiaojian Du default:
628ae7b32e7SXiaojian Du break;
629ae7b32e7SXiaojian Du }
630ae7b32e7SXiaojian Du
631ae7b32e7SXiaojian Du switch (clk_type) {
632ae7b32e7SXiaojian Du case SMU_SOCCLK:
633f02c7336SXiaojian Du case SMU_VCLK:
634f02c7336SXiaojian Du case SMU_DCLK:
635ae7b32e7SXiaojian Du case SMU_MCLK:
636ae7b32e7SXiaojian Du case SMU_FCLK:
637ae7b32e7SXiaojian Du for (i = 0; i < count; i++) {
63863b9acdfSTim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
63963b9acdfSTim Huang ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
640ae7b32e7SXiaojian Du if (ret)
641ae7b32e7SXiaojian Du return ret;
642ae7b32e7SXiaojian Du if (!value)
643ae7b32e7SXiaojian Du continue;
644fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
645ae7b32e7SXiaojian Du cur_value == value ? "*" : "");
646ae7b32e7SXiaojian Du if (cur_value == value)
647ae7b32e7SXiaojian Du cur_value_match_level = true;
648ae7b32e7SXiaojian Du }
649ae7b32e7SXiaojian Du
650ae7b32e7SXiaojian Du if (!cur_value_match_level)
651fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
652ae7b32e7SXiaojian Du break;
653c98ee897SXiaojian Du default:
654c98ee897SXiaojian Du break;
655c98ee897SXiaojian Du }
656c98ee897SXiaojian Du
657c98ee897SXiaojian Du return size;
658c98ee897SXiaojian Du }
659c98ee897SXiaojian Du
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)66086c8236eSXiaojian Du static int vangogh_print_clk_levels(struct smu_context *smu,
66186c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf)
66286c8236eSXiaojian Du {
66386c8236eSXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
66486c8236eSXiaojian Du SmuMetrics_t metrics;
66586c8236eSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
66663b9acdfSTim Huang int i, idx, size = 0, ret = 0;
66786c8236eSXiaojian Du uint32_t cur_value = 0, value = 0, count = 0;
66886c8236eSXiaojian Du bool cur_value_match_level = false;
66948c19a95SPerry Yuan uint32_t min, max;
67086c8236eSXiaojian Du
67186c8236eSXiaojian Du memset(&metrics, 0, sizeof(metrics));
67286c8236eSXiaojian Du
67386c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false);
67486c8236eSXiaojian Du if (ret)
67586c8236eSXiaojian Du return ret;
67686c8236eSXiaojian Du
6778f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size);
6788f48ba30SLang Yu
67986c8236eSXiaojian Du switch (clk_type) {
68086c8236eSXiaojian Du case SMU_OD_SCLK:
68186c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
6828f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
683fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
68486c8236eSXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
685fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
68686c8236eSXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
68786c8236eSXiaojian Du }
68886c8236eSXiaojian Du break;
68986c8236eSXiaojian Du case SMU_OD_CCLK:
69086c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
6918f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
692fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
69386c8236eSXiaojian Du (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
694fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
69586c8236eSXiaojian Du (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
69686c8236eSXiaojian Du }
69786c8236eSXiaojian Du break;
69886c8236eSXiaojian Du case SMU_OD_RANGE:
69986c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
7008f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
701fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
70286c8236eSXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
703fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
70486c8236eSXiaojian Du smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
70586c8236eSXiaojian Du }
70686c8236eSXiaojian Du break;
70786c8236eSXiaojian Du case SMU_SOCCLK:
70886c8236eSXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
70986c8236eSXiaojian Du count = clk_table->NumSocClkLevelsEnabled;
71086c8236eSXiaojian Du cur_value = metrics.Current.SocclkFrequency;
71186c8236eSXiaojian Du break;
71286c8236eSXiaojian Du case SMU_VCLK:
71386c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled;
71486c8236eSXiaojian Du cur_value = metrics.Current.VclkFrequency;
71586c8236eSXiaojian Du break;
71686c8236eSXiaojian Du case SMU_DCLK:
71786c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled;
71886c8236eSXiaojian Du cur_value = metrics.Current.DclkFrequency;
71986c8236eSXiaojian Du break;
72086c8236eSXiaojian Du case SMU_MCLK:
72186c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled;
72286c8236eSXiaojian Du cur_value = metrics.Current.MemclkFrequency;
72386c8236eSXiaojian Du break;
72486c8236eSXiaojian Du case SMU_FCLK:
72586c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled;
72686c8236eSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
72786c8236eSXiaojian Du if (ret)
72886c8236eSXiaojian Du return ret;
72986c8236eSXiaojian Du break;
73048c19a95SPerry Yuan case SMU_GFXCLK:
73148c19a95SPerry Yuan case SMU_SCLK:
73248c19a95SPerry Yuan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
73348c19a95SPerry Yuan if (ret) {
73448c19a95SPerry Yuan return ret;
73548c19a95SPerry Yuan }
73648c19a95SPerry Yuan break;
73786c8236eSXiaojian Du default:
73886c8236eSXiaojian Du break;
73986c8236eSXiaojian Du }
74086c8236eSXiaojian Du
74186c8236eSXiaojian Du switch (clk_type) {
74286c8236eSXiaojian Du case SMU_SOCCLK:
74386c8236eSXiaojian Du case SMU_VCLK:
74486c8236eSXiaojian Du case SMU_DCLK:
74586c8236eSXiaojian Du case SMU_MCLK:
74686c8236eSXiaojian Du case SMU_FCLK:
74786c8236eSXiaojian Du for (i = 0; i < count; i++) {
74863b9acdfSTim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
74963b9acdfSTim Huang ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
75086c8236eSXiaojian Du if (ret)
75186c8236eSXiaojian Du return ret;
75286c8236eSXiaojian Du if (!value)
75386c8236eSXiaojian Du continue;
754fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
75586c8236eSXiaojian Du cur_value == value ? "*" : "");
75686c8236eSXiaojian Du if (cur_value == value)
75786c8236eSXiaojian Du cur_value_match_level = true;
75886c8236eSXiaojian Du }
75986c8236eSXiaojian Du
76086c8236eSXiaojian Du if (!cur_value_match_level)
761fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
76286c8236eSXiaojian Du break;
76348c19a95SPerry Yuan case SMU_GFXCLK:
76448c19a95SPerry Yuan case SMU_SCLK:
76548c19a95SPerry Yuan min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
76648c19a95SPerry Yuan max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
76748c19a95SPerry Yuan if (cur_value == max)
76848c19a95SPerry Yuan i = 2;
76948c19a95SPerry Yuan else if (cur_value == min)
77048c19a95SPerry Yuan i = 0;
77148c19a95SPerry Yuan else
77248c19a95SPerry Yuan i = 1;
77348c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
77448c19a95SPerry Yuan i == 0 ? "*" : "");
77548c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
77648c19a95SPerry Yuan i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
77748c19a95SPerry Yuan i == 1 ? "*" : "");
77848c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
77948c19a95SPerry Yuan i == 2 ? "*" : "");
78048c19a95SPerry Yuan break;
78186c8236eSXiaojian Du default:
78286c8236eSXiaojian Du break;
78386c8236eSXiaojian Du }
78486c8236eSXiaojian Du
78586c8236eSXiaojian Du return size;
78686c8236eSXiaojian Du }
78786c8236eSXiaojian Du
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)78886c8236eSXiaojian Du static int vangogh_common_print_clk_levels(struct smu_context *smu,
78986c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf)
79086c8236eSXiaojian Du {
79186c8236eSXiaojian Du int ret = 0;
79286c8236eSXiaojian Du
793710d9caeSYifan Zhang if (smu->smc_fw_if_version < 0x3)
79486c8236eSXiaojian Du ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
79586c8236eSXiaojian Du else
79686c8236eSXiaojian Du ret = vangogh_print_clk_levels(smu, clk_type, buf);
79786c8236eSXiaojian Du
79886c8236eSXiaojian Du return ret;
79986c8236eSXiaojian Du }
80086c8236eSXiaojian Du
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)801d0e4e112SXiaojian Du static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
802d0e4e112SXiaojian Du enum amd_dpm_forced_level level,
803d0e4e112SXiaojian Du uint32_t *vclk_mask,
804d0e4e112SXiaojian Du uint32_t *dclk_mask,
805d0e4e112SXiaojian Du uint32_t *mclk_mask,
806d0e4e112SXiaojian Du uint32_t *fclk_mask,
807d0e4e112SXiaojian Du uint32_t *soc_mask)
808d0e4e112SXiaojian Du {
809d0e4e112SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
810d0e4e112SXiaojian Du
811307f049bSXiaojian Du if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
812d0e4e112SXiaojian Du if (mclk_mask)
813d0e4e112SXiaojian Du *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
814307f049bSXiaojian Du
815d0e4e112SXiaojian Du if (fclk_mask)
816d0e4e112SXiaojian Du *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
817307f049bSXiaojian Du
818307f049bSXiaojian Du if (soc_mask)
819307f049bSXiaojian Du *soc_mask = 0;
820d0e4e112SXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
821d0e4e112SXiaojian Du if (mclk_mask)
822d0e4e112SXiaojian Du *mclk_mask = 0;
823307f049bSXiaojian Du
824d0e4e112SXiaojian Du if (fclk_mask)
825d0e4e112SXiaojian Du *fclk_mask = 0;
826d0e4e112SXiaojian Du
827d0e4e112SXiaojian Du if (soc_mask)
828307f049bSXiaojian Du *soc_mask = 1;
829307f049bSXiaojian Du
830307f049bSXiaojian Du if (vclk_mask)
831307f049bSXiaojian Du *vclk_mask = 1;
832307f049bSXiaojian Du
833307f049bSXiaojian Du if (dclk_mask)
834307f049bSXiaojian Du *dclk_mask = 1;
835307f049bSXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
836307f049bSXiaojian Du if (mclk_mask)
837307f049bSXiaojian Du *mclk_mask = 0;
838307f049bSXiaojian Du
839307f049bSXiaojian Du if (fclk_mask)
840307f049bSXiaojian Du *fclk_mask = 0;
841307f049bSXiaojian Du
842307f049bSXiaojian Du if (soc_mask)
843307f049bSXiaojian Du *soc_mask = 1;
844307f049bSXiaojian Du
845307f049bSXiaojian Du if (vclk_mask)
846307f049bSXiaojian Du *vclk_mask = 1;
847307f049bSXiaojian Du
848307f049bSXiaojian Du if (dclk_mask)
849307f049bSXiaojian Du *dclk_mask = 1;
850d0e4e112SXiaojian Du }
851d0e4e112SXiaojian Du
852d0e4e112SXiaojian Du return 0;
853d0e4e112SXiaojian Du }
854d0e4e112SXiaojian Du
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)8558f8150faSSouptick Joarder static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
856d0e4e112SXiaojian Du enum smu_clk_type clk_type)
857d0e4e112SXiaojian Du {
858d0e4e112SXiaojian Du enum smu_feature_mask feature_id = 0;
859d0e4e112SXiaojian Du
860d0e4e112SXiaojian Du switch (clk_type) {
861d0e4e112SXiaojian Du case SMU_MCLK:
862d0e4e112SXiaojian Du case SMU_UCLK:
863d0e4e112SXiaojian Du case SMU_FCLK:
864d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_FCLK_BIT;
865d0e4e112SXiaojian Du break;
866d0e4e112SXiaojian Du case SMU_GFXCLK:
867d0e4e112SXiaojian Du case SMU_SCLK:
868d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
869d0e4e112SXiaojian Du break;
870d0e4e112SXiaojian Du case SMU_SOCCLK:
871d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
872d0e4e112SXiaojian Du break;
873d0e4e112SXiaojian Du case SMU_VCLK:
874d0e4e112SXiaojian Du case SMU_DCLK:
875d0e4e112SXiaojian Du feature_id = SMU_FEATURE_VCN_DPM_BIT;
876d0e4e112SXiaojian Du break;
877d0e4e112SXiaojian Du default:
878d0e4e112SXiaojian Du return true;
879d0e4e112SXiaojian Du }
880d0e4e112SXiaojian Du
881d0e4e112SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, feature_id))
882d0e4e112SXiaojian Du return false;
883d0e4e112SXiaojian Du
884d0e4e112SXiaojian Du return true;
885d0e4e112SXiaojian Du }
886d0e4e112SXiaojian Du
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)887d0e4e112SXiaojian Du static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
888d0e4e112SXiaojian Du enum smu_clk_type clk_type,
889d0e4e112SXiaojian Du uint32_t *min,
890d0e4e112SXiaojian Du uint32_t *max)
891d0e4e112SXiaojian Du {
892d0e4e112SXiaojian Du int ret = 0;
893d0e4e112SXiaojian Du uint32_t soc_mask;
894d0e4e112SXiaojian Du uint32_t vclk_mask;
895d0e4e112SXiaojian Du uint32_t dclk_mask;
896d0e4e112SXiaojian Du uint32_t mclk_mask;
897d0e4e112SXiaojian Du uint32_t fclk_mask;
898d0e4e112SXiaojian Du uint32_t clock_limit;
899d0e4e112SXiaojian Du
900d0e4e112SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
901d0e4e112SXiaojian Du switch (clk_type) {
902d0e4e112SXiaojian Du case SMU_MCLK:
903d0e4e112SXiaojian Du case SMU_UCLK:
904d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.uclk;
905d0e4e112SXiaojian Du break;
906d0e4e112SXiaojian Du case SMU_FCLK:
907d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.fclk;
908d0e4e112SXiaojian Du break;
909d0e4e112SXiaojian Du case SMU_GFXCLK:
910d0e4e112SXiaojian Du case SMU_SCLK:
911d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.gfxclk;
912d0e4e112SXiaojian Du break;
913d0e4e112SXiaojian Du case SMU_SOCCLK:
914d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.socclk;
915d0e4e112SXiaojian Du break;
916d0e4e112SXiaojian Du case SMU_VCLK:
917d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.vclk;
918d0e4e112SXiaojian Du break;
919d0e4e112SXiaojian Du case SMU_DCLK:
920d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.dclk;
921d0e4e112SXiaojian Du break;
922d0e4e112SXiaojian Du default:
923d0e4e112SXiaojian Du clock_limit = 0;
924d0e4e112SXiaojian Du break;
925d0e4e112SXiaojian Du }
926d0e4e112SXiaojian Du
927d0e4e112SXiaojian Du /* clock in Mhz unit */
928d0e4e112SXiaojian Du if (min)
929d0e4e112SXiaojian Du *min = clock_limit / 100;
930d0e4e112SXiaojian Du if (max)
931d0e4e112SXiaojian Du *max = clock_limit / 100;
932d0e4e112SXiaojian Du
933d0e4e112SXiaojian Du return 0;
934d0e4e112SXiaojian Du }
935d0e4e112SXiaojian Du if (max) {
936d0e4e112SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu,
937d0e4e112SXiaojian Du AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
938d0e4e112SXiaojian Du &vclk_mask,
939d0e4e112SXiaojian Du &dclk_mask,
940d0e4e112SXiaojian Du &mclk_mask,
941d0e4e112SXiaojian Du &fclk_mask,
942d0e4e112SXiaojian Du &soc_mask);
943d0e4e112SXiaojian Du if (ret)
944d0e4e112SXiaojian Du goto failed;
945d0e4e112SXiaojian Du
946d0e4e112SXiaojian Du switch (clk_type) {
947d0e4e112SXiaojian Du case SMU_UCLK:
948d0e4e112SXiaojian Du case SMU_MCLK:
949d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
950d0e4e112SXiaojian Du if (ret)
951d0e4e112SXiaojian Du goto failed;
952d0e4e112SXiaojian Du break;
953d0e4e112SXiaojian Du case SMU_SOCCLK:
954d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
955d0e4e112SXiaojian Du if (ret)
956d0e4e112SXiaojian Du goto failed;
957d0e4e112SXiaojian Du break;
958d0e4e112SXiaojian Du case SMU_FCLK:
959d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
960d0e4e112SXiaojian Du if (ret)
961d0e4e112SXiaojian Du goto failed;
962d0e4e112SXiaojian Du break;
963d0e4e112SXiaojian Du case SMU_VCLK:
964d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
965d0e4e112SXiaojian Du if (ret)
966d0e4e112SXiaojian Du goto failed;
967d0e4e112SXiaojian Du break;
968d0e4e112SXiaojian Du case SMU_DCLK:
969d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
970d0e4e112SXiaojian Du if (ret)
971d0e4e112SXiaojian Du goto failed;
972d0e4e112SXiaojian Du break;
973d0e4e112SXiaojian Du default:
974d0e4e112SXiaojian Du ret = -EINVAL;
975d0e4e112SXiaojian Du goto failed;
976d0e4e112SXiaojian Du }
977d0e4e112SXiaojian Du }
978d0e4e112SXiaojian Du if (min) {
979*b2871de6STim Huang ret = vangogh_get_profiling_clk_mask(smu,
980*b2871de6STim Huang AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
981*b2871de6STim Huang NULL,
982*b2871de6STim Huang NULL,
983*b2871de6STim Huang &mclk_mask,
984*b2871de6STim Huang &fclk_mask,
985*b2871de6STim Huang &soc_mask);
986*b2871de6STim Huang if (ret)
987*b2871de6STim Huang goto failed;
988*b2871de6STim Huang
989*b2871de6STim Huang vclk_mask = dclk_mask = 0;
990*b2871de6STim Huang
991d0e4e112SXiaojian Du switch (clk_type) {
992d0e4e112SXiaojian Du case SMU_UCLK:
993d0e4e112SXiaojian Du case SMU_MCLK:
994d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
995d0e4e112SXiaojian Du if (ret)
996d0e4e112SXiaojian Du goto failed;
997d0e4e112SXiaojian Du break;
998d0e4e112SXiaojian Du case SMU_SOCCLK:
999d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
1000d0e4e112SXiaojian Du if (ret)
1001d0e4e112SXiaojian Du goto failed;
1002d0e4e112SXiaojian Du break;
1003d0e4e112SXiaojian Du case SMU_FCLK:
1004d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1005d0e4e112SXiaojian Du if (ret)
1006d0e4e112SXiaojian Du goto failed;
1007d0e4e112SXiaojian Du break;
1008d0e4e112SXiaojian Du case SMU_VCLK:
1009d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1010d0e4e112SXiaojian Du if (ret)
1011d0e4e112SXiaojian Du goto failed;
1012d0e4e112SXiaojian Du break;
1013d0e4e112SXiaojian Du case SMU_DCLK:
1014d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1015d0e4e112SXiaojian Du if (ret)
1016d0e4e112SXiaojian Du goto failed;
1017d0e4e112SXiaojian Du break;
1018d0e4e112SXiaojian Du default:
1019d0e4e112SXiaojian Du ret = -EINVAL;
1020d0e4e112SXiaojian Du goto failed;
1021d0e4e112SXiaojian Du }
1022d0e4e112SXiaojian Du }
1023d0e4e112SXiaojian Du failed:
1024d0e4e112SXiaojian Du return ret;
1025d0e4e112SXiaojian Du }
1026d0e4e112SXiaojian Du
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1027307f049bSXiaojian Du static int vangogh_get_power_profile_mode(struct smu_context *smu,
1028307f049bSXiaojian Du char *buf)
1029307f049bSXiaojian Du {
1030307f049bSXiaojian Du uint32_t i, size = 0;
1031307f049bSXiaojian Du int16_t workload_type = 0;
1032307f049bSXiaojian Du
1033307f049bSXiaojian Du if (!buf)
1034307f049bSXiaojian Du return -EINVAL;
1035307f049bSXiaojian Du
1036dc622367SPerry Yuan for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1037307f049bSXiaojian Du /*
1038307f049bSXiaojian Du * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1039307f049bSXiaojian Du * Not all profile modes are supported on vangogh.
1040307f049bSXiaojian Du */
1041307f049bSXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu,
1042307f049bSXiaojian Du CMN2ASIC_MAPPING_WORKLOAD,
1043307f049bSXiaojian Du i);
1044307f049bSXiaojian Du
1045307f049bSXiaojian Du if (workload_type < 0)
1046307f049bSXiaojian Du continue;
1047307f049bSXiaojian Du
1048fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
104994a80b5bSDarren Powell i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1050307f049bSXiaojian Du }
1051307f049bSXiaojian Du
1052307f049bSXiaojian Du return size;
1053307f049bSXiaojian Du }
1054307f049bSXiaojian Du
vangogh_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1055d0e4e112SXiaojian Du static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1056d0e4e112SXiaojian Du {
1057d0e4e112SXiaojian Du int workload_type, ret;
1058d0e4e112SXiaojian Du uint32_t profile_mode = input[size];
1059d0e4e112SXiaojian Du
1060dc622367SPerry Yuan if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
1061d0e4e112SXiaojian Du dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1062d0e4e112SXiaojian Du return -EINVAL;
1063d0e4e112SXiaojian Du }
1064d0e4e112SXiaojian Du
1065f727ebebSXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1066f727ebebSXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1067f727ebebSXiaojian Du return 0;
1068f727ebebSXiaojian Du
1069d0e4e112SXiaojian Du /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1070d0e4e112SXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu,
1071d0e4e112SXiaojian Du CMN2ASIC_MAPPING_WORKLOAD,
1072d0e4e112SXiaojian Du profile_mode);
1073d0e4e112SXiaojian Du if (workload_type < 0) {
10749d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1075d0e4e112SXiaojian Du profile_mode);
1076d0e4e112SXiaojian Du return -EINVAL;
1077d0e4e112SXiaojian Du }
1078d0e4e112SXiaojian Du
1079d0e4e112SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1080d0e4e112SXiaojian Du 1 << workload_type,
1081d0e4e112SXiaojian Du NULL);
1082d0e4e112SXiaojian Du if (ret) {
1083d0e4e112SXiaojian Du dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1084d0e4e112SXiaojian Du workload_type);
1085d0e4e112SXiaojian Du return ret;
1086d0e4e112SXiaojian Du }
1087d0e4e112SXiaojian Du
1088d0e4e112SXiaojian Du smu->power_profile_mode = profile_mode;
1089d0e4e112SXiaojian Du
1090d0e4e112SXiaojian Du return 0;
1091d0e4e112SXiaojian Du }
1092d0e4e112SXiaojian Du
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1093dd9e0b21SXiaojian Du static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1094dd9e0b21SXiaojian Du enum smu_clk_type clk_type,
1095dd9e0b21SXiaojian Du uint32_t min,
1096dd9e0b21SXiaojian Du uint32_t max)
1097dd9e0b21SXiaojian Du {
1098dd9e0b21SXiaojian Du int ret = 0;
1099dd9e0b21SXiaojian Du
1100dd9e0b21SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1101dd9e0b21SXiaojian Du return 0;
1102dd9e0b21SXiaojian Du
1103dd9e0b21SXiaojian Du switch (clk_type) {
1104dd9e0b21SXiaojian Du case SMU_GFXCLK:
1105dd9e0b21SXiaojian Du case SMU_SCLK:
1106dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1107dd9e0b21SXiaojian Du SMU_MSG_SetHardMinGfxClk,
1108dd9e0b21SXiaojian Du min, NULL);
1109dd9e0b21SXiaojian Du if (ret)
1110dd9e0b21SXiaojian Du return ret;
1111dd9e0b21SXiaojian Du
1112dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1113dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxGfxClk,
1114dd9e0b21SXiaojian Du max, NULL);
1115dd9e0b21SXiaojian Du if (ret)
1116dd9e0b21SXiaojian Du return ret;
1117dd9e0b21SXiaojian Du break;
1118dd9e0b21SXiaojian Du case SMU_FCLK:
1119dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1120dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq,
1121dd9e0b21SXiaojian Du min, NULL);
1122dd9e0b21SXiaojian Du if (ret)
1123dd9e0b21SXiaojian Du return ret;
1124dd9e0b21SXiaojian Du
1125dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1126dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq,
1127dd9e0b21SXiaojian Du max, NULL);
1128dd9e0b21SXiaojian Du if (ret)
1129dd9e0b21SXiaojian Du return ret;
1130dd9e0b21SXiaojian Du break;
1131dd9e0b21SXiaojian Du case SMU_SOCCLK:
1132dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1133dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq,
1134dd9e0b21SXiaojian Du min, NULL);
1135dd9e0b21SXiaojian Du if (ret)
1136dd9e0b21SXiaojian Du return ret;
1137dd9e0b21SXiaojian Du
1138dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1139dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq,
1140dd9e0b21SXiaojian Du max, NULL);
1141dd9e0b21SXiaojian Du if (ret)
1142dd9e0b21SXiaojian Du return ret;
1143dd9e0b21SXiaojian Du break;
1144dd9e0b21SXiaojian Du case SMU_VCLK:
1145dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1146dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1147dd9e0b21SXiaojian Du min << 16, NULL);
1148dd9e0b21SXiaojian Du if (ret)
1149dd9e0b21SXiaojian Du return ret;
1150dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1151dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn,
1152dd9e0b21SXiaojian Du max << 16, NULL);
1153dd9e0b21SXiaojian Du if (ret)
1154dd9e0b21SXiaojian Du return ret;
1155dd9e0b21SXiaojian Du break;
1156dd9e0b21SXiaojian Du case SMU_DCLK:
1157dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1158dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1159dd9e0b21SXiaojian Du min, NULL);
1160dd9e0b21SXiaojian Du if (ret)
1161dd9e0b21SXiaojian Du return ret;
1162dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1163dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn,
1164dd9e0b21SXiaojian Du max, NULL);
1165dd9e0b21SXiaojian Du if (ret)
1166dd9e0b21SXiaojian Du return ret;
1167dd9e0b21SXiaojian Du break;
1168dd9e0b21SXiaojian Du default:
1169dd9e0b21SXiaojian Du return -EINVAL;
1170dd9e0b21SXiaojian Du }
1171dd9e0b21SXiaojian Du
1172dd9e0b21SXiaojian Du return ret;
1173dd9e0b21SXiaojian Du }
1174dd9e0b21SXiaojian Du
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1175dd9e0b21SXiaojian Du static int vangogh_force_clk_levels(struct smu_context *smu,
1176dd9e0b21SXiaojian Du enum smu_clk_type clk_type, uint32_t mask)
1177dd9e0b21SXiaojian Du {
1178dd9e0b21SXiaojian Du uint32_t soft_min_level = 0, soft_max_level = 0;
1179dd9e0b21SXiaojian Du uint32_t min_freq = 0, max_freq = 0;
1180dd9e0b21SXiaojian Du int ret = 0 ;
1181dd9e0b21SXiaojian Du
1182dd9e0b21SXiaojian Du soft_min_level = mask ? (ffs(mask) - 1) : 0;
1183dd9e0b21SXiaojian Du soft_max_level = mask ? (fls(mask) - 1) : 0;
1184dd9e0b21SXiaojian Du
1185dd9e0b21SXiaojian Du switch (clk_type) {
1186dd9e0b21SXiaojian Du case SMU_SOCCLK:
1187dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1188dd9e0b21SXiaojian Du soft_min_level, &min_freq);
1189dd9e0b21SXiaojian Du if (ret)
1190dd9e0b21SXiaojian Du return ret;
1191dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1192dd9e0b21SXiaojian Du soft_max_level, &max_freq);
1193dd9e0b21SXiaojian Du if (ret)
1194dd9e0b21SXiaojian Du return ret;
1195dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1196dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq,
1197dd9e0b21SXiaojian Du max_freq, NULL);
1198dd9e0b21SXiaojian Du if (ret)
1199dd9e0b21SXiaojian Du return ret;
1200dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1201dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq,
1202dd9e0b21SXiaojian Du min_freq, NULL);
1203dd9e0b21SXiaojian Du if (ret)
1204dd9e0b21SXiaojian Du return ret;
1205dd9e0b21SXiaojian Du break;
1206dd9e0b21SXiaojian Du case SMU_FCLK:
1207dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1208dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1209dd9e0b21SXiaojian Du if (ret)
1210dd9e0b21SXiaojian Du return ret;
1211dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1212dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1213dd9e0b21SXiaojian Du if (ret)
1214dd9e0b21SXiaojian Du return ret;
1215dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1216dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq,
1217dd9e0b21SXiaojian Du max_freq, NULL);
1218dd9e0b21SXiaojian Du if (ret)
1219dd9e0b21SXiaojian Du return ret;
1220dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1221dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq,
1222dd9e0b21SXiaojian Du min_freq, NULL);
1223dd9e0b21SXiaojian Du if (ret)
1224dd9e0b21SXiaojian Du return ret;
1225dd9e0b21SXiaojian Du break;
1226dd9e0b21SXiaojian Du case SMU_VCLK:
1227dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1228dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1229dd9e0b21SXiaojian Du if (ret)
1230dd9e0b21SXiaojian Du return ret;
1231307f049bSXiaojian Du
1232dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1233dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1234dd9e0b21SXiaojian Du if (ret)
1235dd9e0b21SXiaojian Du return ret;
1236307f049bSXiaojian Du
1237307f049bSXiaojian Du
1238dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1239dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1240dd9e0b21SXiaojian Du min_freq << 16, NULL);
1241dd9e0b21SXiaojian Du if (ret)
1242dd9e0b21SXiaojian Du return ret;
1243307f049bSXiaojian Du
1244307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1245307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn,
1246307f049bSXiaojian Du max_freq << 16, NULL);
1247307f049bSXiaojian Du if (ret)
1248307f049bSXiaojian Du return ret;
1249307f049bSXiaojian Du
1250dd9e0b21SXiaojian Du break;
1251dd9e0b21SXiaojian Du case SMU_DCLK:
1252dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1253dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1254dd9e0b21SXiaojian Du if (ret)
1255dd9e0b21SXiaojian Du return ret;
1256307f049bSXiaojian Du
1257dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1258dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1259dd9e0b21SXiaojian Du if (ret)
1260dd9e0b21SXiaojian Du return ret;
1261307f049bSXiaojian Du
1262dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1263dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1264dd9e0b21SXiaojian Du min_freq, NULL);
1265dd9e0b21SXiaojian Du if (ret)
1266dd9e0b21SXiaojian Du return ret;
1267307f049bSXiaojian Du
1268307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1269307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn,
1270307f049bSXiaojian Du max_freq, NULL);
1271307f049bSXiaojian Du if (ret)
1272307f049bSXiaojian Du return ret;
1273307f049bSXiaojian Du
1274dd9e0b21SXiaojian Du break;
1275dd9e0b21SXiaojian Du default:
1276dd9e0b21SXiaojian Du break;
1277dd9e0b21SXiaojian Du }
1278dd9e0b21SXiaojian Du
1279dd9e0b21SXiaojian Du return ret;
1280dd9e0b21SXiaojian Du }
1281dd9e0b21SXiaojian Du
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1282dd9e0b21SXiaojian Du static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1283dd9e0b21SXiaojian Du {
1284dd9e0b21SXiaojian Du int ret = 0, i = 0;
1285dd9e0b21SXiaojian Du uint32_t min_freq, max_freq, force_freq;
1286dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1287dd9e0b21SXiaojian Du
1288dd9e0b21SXiaojian Du enum smu_clk_type clks[] = {
1289dd9e0b21SXiaojian Du SMU_SOCCLK,
1290dd9e0b21SXiaojian Du SMU_VCLK,
1291dd9e0b21SXiaojian Du SMU_DCLK,
1292dd9e0b21SXiaojian Du SMU_FCLK,
1293dd9e0b21SXiaojian Du };
1294dd9e0b21SXiaojian Du
1295dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clks); i++) {
1296dd9e0b21SXiaojian Du clk_type = clks[i];
1297dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1298dd9e0b21SXiaojian Du if (ret)
1299dd9e0b21SXiaojian Du return ret;
1300dd9e0b21SXiaojian Du
1301dd9e0b21SXiaojian Du force_freq = highest ? max_freq : min_freq;
1302dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1303dd9e0b21SXiaojian Du if (ret)
1304dd9e0b21SXiaojian Du return ret;
1305dd9e0b21SXiaojian Du }
1306dd9e0b21SXiaojian Du
1307dd9e0b21SXiaojian Du return ret;
1308dd9e0b21SXiaojian Du }
1309dd9e0b21SXiaojian Du
vangogh_unforce_dpm_levels(struct smu_context * smu)1310dd9e0b21SXiaojian Du static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1311dd9e0b21SXiaojian Du {
1312dd9e0b21SXiaojian Du int ret = 0, i = 0;
1313dd9e0b21SXiaojian Du uint32_t min_freq, max_freq;
1314dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1315dd9e0b21SXiaojian Du
1316dd9e0b21SXiaojian Du struct clk_feature_map {
1317dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1318dd9e0b21SXiaojian Du uint32_t feature;
1319dd9e0b21SXiaojian Du } clk_feature_map[] = {
1320dd9e0b21SXiaojian Du {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1321dd9e0b21SXiaojian Du {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1322b0eec124SXiaojian Du {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1323b0eec124SXiaojian Du {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1324dd9e0b21SXiaojian Du };
1325dd9e0b21SXiaojian Du
1326dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1327dd9e0b21SXiaojian Du
1328dd9e0b21SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1329dd9e0b21SXiaojian Du continue;
1330dd9e0b21SXiaojian Du
1331dd9e0b21SXiaojian Du clk_type = clk_feature_map[i].clk_type;
1332dd9e0b21SXiaojian Du
1333dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1334dd9e0b21SXiaojian Du
1335dd9e0b21SXiaojian Du if (ret)
1336dd9e0b21SXiaojian Du return ret;
1337dd9e0b21SXiaojian Du
1338dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1339dd9e0b21SXiaojian Du
1340dd9e0b21SXiaojian Du if (ret)
1341dd9e0b21SXiaojian Du return ret;
1342dd9e0b21SXiaojian Du }
1343dd9e0b21SXiaojian Du
1344dd9e0b21SXiaojian Du return ret;
1345dd9e0b21SXiaojian Du }
1346dd9e0b21SXiaojian Du
vangogh_set_peak_clock_by_device(struct smu_context * smu)1347dd9e0b21SXiaojian Du static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1348dd9e0b21SXiaojian Du {
1349dd9e0b21SXiaojian Du int ret = 0;
1350dd9e0b21SXiaojian Du uint32_t socclk_freq = 0, fclk_freq = 0;
1351307f049bSXiaojian Du uint32_t vclk_freq = 0, dclk_freq = 0;
1352dd9e0b21SXiaojian Du
1353dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1354dd9e0b21SXiaojian Du if (ret)
1355dd9e0b21SXiaojian Du return ret;
1356dd9e0b21SXiaojian Du
1357dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1358dd9e0b21SXiaojian Du if (ret)
1359dd9e0b21SXiaojian Du return ret;
1360dd9e0b21SXiaojian Du
1361dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1362dd9e0b21SXiaojian Du if (ret)
1363dd9e0b21SXiaojian Du return ret;
1364dd9e0b21SXiaojian Du
1365dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1366dd9e0b21SXiaojian Du if (ret)
1367dd9e0b21SXiaojian Du return ret;
1368dd9e0b21SXiaojian Du
1369307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1370307f049bSXiaojian Du if (ret)
1371307f049bSXiaojian Du return ret;
1372307f049bSXiaojian Du
1373307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1374307f049bSXiaojian Du if (ret)
1375307f049bSXiaojian Du return ret;
1376307f049bSXiaojian Du
1377307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1378307f049bSXiaojian Du if (ret)
1379307f049bSXiaojian Du return ret;
1380307f049bSXiaojian Du
1381307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1382307f049bSXiaojian Du if (ret)
1383307f049bSXiaojian Du return ret;
1384307f049bSXiaojian Du
1385dd9e0b21SXiaojian Du return ret;
1386dd9e0b21SXiaojian Du }
1387dd9e0b21SXiaojian Du
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1388ea173d15SXiaojian Du static int vangogh_set_performance_level(struct smu_context *smu,
1389ea173d15SXiaojian Du enum amd_dpm_forced_level level)
1390ea173d15SXiaojian Du {
139191aa9c8fSAlex Deucher int ret = 0, i;
1392ea173d15SXiaojian Du uint32_t soc_mask, mclk_mask, fclk_mask;
1393307f049bSXiaojian Du uint32_t vclk_mask = 0, dclk_mask = 0;
1394ea173d15SXiaojian Du
1395d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1396d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1397d7379efaSXiaojian Du
139868e3871dSAlex Deucher switch (level) {
139968e3871dSAlex Deucher case AMD_DPM_FORCED_LEVEL_HIGH:
140068e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
140168e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
140268e3871dSAlex Deucher
140368e3871dSAlex Deucher
1404ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, true);
140568e3871dSAlex Deucher if (ret)
140668e3871dSAlex Deucher return ret;
1407ea173d15SXiaojian Du break;
1408ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_LOW:
1409d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
141068e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1411d7379efaSXiaojian Du
1412ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, false);
141368e3871dSAlex Deucher if (ret)
141468e3871dSAlex Deucher return ret;
1415ea173d15SXiaojian Du break;
1416ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_AUTO:
1417d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1418d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1419d7379efaSXiaojian Du
1420ea173d15SXiaojian Du ret = vangogh_unforce_dpm_levels(smu);
142168e3871dSAlex Deucher if (ret)
142268e3871dSAlex Deucher return ret;
1423ea173d15SXiaojian Du break;
1424ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
142568e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
142668e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1427307f049bSXiaojian Du
1428307f049bSXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level,
1429307f049bSXiaojian Du &vclk_mask,
1430307f049bSXiaojian Du &dclk_mask,
1431307f049bSXiaojian Du &mclk_mask,
1432307f049bSXiaojian Du &fclk_mask,
1433307f049bSXiaojian Du &soc_mask);
1434307f049bSXiaojian Du if (ret)
1435307f049bSXiaojian Du return ret;
1436307f049bSXiaojian Du
1437307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1438307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1439307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1440307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1441ea173d15SXiaojian Du break;
1442ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1443d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
144468e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1445ea173d15SXiaojian Du break;
1446ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1447d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1448d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1449d7379efaSXiaojian Du
1450ea173d15SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level,
1451ea173d15SXiaojian Du NULL,
1452ea173d15SXiaojian Du NULL,
1453ea173d15SXiaojian Du &mclk_mask,
1454ea173d15SXiaojian Du &fclk_mask,
1455307f049bSXiaojian Du NULL);
1456ea173d15SXiaojian Du if (ret)
1457ea173d15SXiaojian Du return ret;
1458307f049bSXiaojian Du
1459ea173d15SXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1460ea173d15SXiaojian Du break;
1461ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
146268e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
146368e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1464307f049bSXiaojian Du
1465ea173d15SXiaojian Du ret = vangogh_set_peak_clock_by_device(smu);
146668e3871dSAlex Deucher if (ret)
146768e3871dSAlex Deucher return ret;
1468ea173d15SXiaojian Du break;
1469ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_MANUAL:
1470ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1471ea173d15SXiaojian Du default:
147268e3871dSAlex Deucher return 0;
1473ea173d15SXiaojian Du }
147468e3871dSAlex Deucher
147568e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
147668e3871dSAlex Deucher smu->gfx_actual_hard_min_freq, NULL);
147768e3871dSAlex Deucher if (ret)
147868e3871dSAlex Deucher return ret;
147968e3871dSAlex Deucher
148068e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
148168e3871dSAlex Deucher smu->gfx_actual_soft_max_freq, NULL);
148268e3871dSAlex Deucher if (ret)
148368e3871dSAlex Deucher return ret;
148468e3871dSAlex Deucher
148591aa9c8fSAlex Deucher if (smu->adev->pm.fw_version >= 0x43f1b00) {
148691aa9c8fSAlex Deucher for (i = 0; i < smu->cpu_core_num; i++) {
148791aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
148891aa9c8fSAlex Deucher ((i << 20)
148991aa9c8fSAlex Deucher | smu->cpu_actual_soft_min_freq),
149091aa9c8fSAlex Deucher NULL);
149191aa9c8fSAlex Deucher if (ret)
149291aa9c8fSAlex Deucher return ret;
149391aa9c8fSAlex Deucher
149491aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
149591aa9c8fSAlex Deucher ((i << 20)
149691aa9c8fSAlex Deucher | smu->cpu_actual_soft_max_freq),
149791aa9c8fSAlex Deucher NULL);
149891aa9c8fSAlex Deucher if (ret)
149991aa9c8fSAlex Deucher return ret;
150091aa9c8fSAlex Deucher }
150191aa9c8fSAlex Deucher }
150291aa9c8fSAlex Deucher
1503ea173d15SXiaojian Du return ret;
1504ea173d15SXiaojian Du }
1505ea173d15SXiaojian Du
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1506271ab489SXiaojian Du static int vangogh_read_sensor(struct smu_context *smu,
1507271ab489SXiaojian Du enum amd_pp_sensors sensor,
1508271ab489SXiaojian Du void *data, uint32_t *size)
1509271ab489SXiaojian Du {
1510271ab489SXiaojian Du int ret = 0;
1511271ab489SXiaojian Du
1512271ab489SXiaojian Du if (!data || !size)
1513271ab489SXiaojian Du return -EINVAL;
1514271ab489SXiaojian Du
1515271ab489SXiaojian Du switch (sensor) {
1516271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_LOAD:
151786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15186cc24d8dSAlex Deucher METRICS_AVERAGE_GFXACTIVITY,
15196cc24d8dSAlex Deucher (uint32_t *)data);
1520271ab489SXiaojian Du *size = 4;
1521271ab489SXiaojian Du break;
15222a88f1b5SXiaojian Du case AMDGPU_PP_SENSOR_VCN_LOAD:
15232a88f1b5SXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15242a88f1b5SXiaojian Du METRICS_AVERAGE_VCNACTIVITY,
15252a88f1b5SXiaojian Du (uint32_t *)data);
15262a88f1b5SXiaojian Du *size = 4;
15272a88f1b5SXiaojian Du break;
15289366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
152986c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15306cc24d8dSAlex Deucher METRICS_AVERAGE_SOCKETPOWER,
15316cc24d8dSAlex Deucher (uint32_t *)data);
1532271ab489SXiaojian Du *size = 4;
1533271ab489SXiaojian Du break;
153447f1724dSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
153547f1724dSMario Limonciello ret = vangogh_common_get_smu_metrics_data(smu,
153647f1724dSMario Limonciello METRICS_CURR_SOCKETPOWER,
153747f1724dSMario Limonciello (uint32_t *)data);
153847f1724dSMario Limonciello *size = 4;
153947f1724dSMario Limonciello break;
1540271ab489SXiaojian Du case AMDGPU_PP_SENSOR_EDGE_TEMP:
154186c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15426cc24d8dSAlex Deucher METRICS_TEMPERATURE_EDGE,
15436cc24d8dSAlex Deucher (uint32_t *)data);
15446cc24d8dSAlex Deucher *size = 4;
15456cc24d8dSAlex Deucher break;
1546271ab489SXiaojian Du case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
154786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15486cc24d8dSAlex Deucher METRICS_TEMPERATURE_HOTSPOT,
15496cc24d8dSAlex Deucher (uint32_t *)data);
1550271ab489SXiaojian Du *size = 4;
1551271ab489SXiaojian Du break;
1552271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_MCLK:
155386c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1554a99a5116SXiaojian Du METRICS_CURR_UCLK,
15556cc24d8dSAlex Deucher (uint32_t *)data);
1556271ab489SXiaojian Du *(uint32_t *)data *= 100;
1557271ab489SXiaojian Du *size = 4;
1558271ab489SXiaojian Du break;
1559271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_SCLK:
156086c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1561a99a5116SXiaojian Du METRICS_CURR_GFXCLK,
15626cc24d8dSAlex Deucher (uint32_t *)data);
1563271ab489SXiaojian Du *(uint32_t *)data *= 100;
1564271ab489SXiaojian Du *size = 4;
1565271ab489SXiaojian Du break;
1566271ab489SXiaojian Du case AMDGPU_PP_SENSOR_VDDGFX:
156786c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15682139d12bSAlex Deucher METRICS_VOLTAGE_VDDGFX,
15692139d12bSAlex Deucher (uint32_t *)data);
15702139d12bSAlex Deucher *size = 4;
15712139d12bSAlex Deucher break;
15722139d12bSAlex Deucher case AMDGPU_PP_SENSOR_VDDNB:
157386c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15742139d12bSAlex Deucher METRICS_VOLTAGE_VDDSOC,
15752139d12bSAlex Deucher (uint32_t *)data);
1576271ab489SXiaojian Du *size = 4;
1577271ab489SXiaojian Du break;
1578517cb957SHuang Rui case AMDGPU_PP_SENSOR_CPU_CLK:
157986c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1580517cb957SHuang Rui METRICS_AVERAGE_CPUCLK,
1581517cb957SHuang Rui (uint32_t *)data);
15824aef0ebcSHuang Rui *size = smu->cpu_core_num * sizeof(uint16_t);
1583517cb957SHuang Rui break;
1584271ab489SXiaojian Du default:
1585271ab489SXiaojian Du ret = -EOPNOTSUPP;
1586271ab489SXiaojian Du break;
1587271ab489SXiaojian Du }
1588271ab489SXiaojian Du
1589271ab489SXiaojian Du return ret;
1590271ab489SXiaojian Du }
1591271ab489SXiaojian Du
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)15920c3c9936SKun Liu static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
15930c3c9936SKun Liu {
15940c3c9936SKun Liu return smu_cmn_send_smc_msg_with_param(smu,
15950c3c9936SKun Liu SMU_MSG_GetThermalLimit,
15960c3c9936SKun Liu 0, limit);
15970c3c9936SKun Liu }
15980c3c9936SKun Liu
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1599aea9040cSKun Liu static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
16000c3c9936SKun Liu {
16010c3c9936SKun Liu return smu_cmn_send_smc_msg_with_param(smu,
16020c3c9936SKun Liu SMU_MSG_SetReducedThermalLimit,
16030c3c9936SKun Liu limit, NULL);
16040c3c9936SKun Liu }
16050c3c9936SKun Liu
16060c3c9936SKun Liu
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1607271ab489SXiaojian Du static int vangogh_set_watermarks_table(struct smu_context *smu,
1608271ab489SXiaojian Du struct pp_smu_wm_range_sets *clock_ranges)
1609271ab489SXiaojian Du {
1610271ab489SXiaojian Du int i;
1611271ab489SXiaojian Du int ret = 0;
1612271ab489SXiaojian Du Watermarks_t *table = smu->smu_table.watermarks_table;
1613271ab489SXiaojian Du
1614271ab489SXiaojian Du if (!table || !clock_ranges)
1615271ab489SXiaojian Du return -EINVAL;
1616271ab489SXiaojian Du
1617271ab489SXiaojian Du if (clock_ranges) {
1618271ab489SXiaojian Du if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1619271ab489SXiaojian Du clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1620271ab489SXiaojian Du return -EINVAL;
1621271ab489SXiaojian Du
1622271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1623271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinClock =
1624271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1625271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1626271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1627271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1628271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1629271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1630271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1631271ab489SXiaojian Du
1632271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1633271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].wm_inst;
1634271ab489SXiaojian Du }
1635271ab489SXiaojian Du
1636271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1637271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinClock =
1638271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1639271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1640271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1641271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1642271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1643271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1644271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1645271ab489SXiaojian Du
1646271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1647271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].wm_inst;
1648271ab489SXiaojian Du }
1649271ab489SXiaojian Du
1650271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_EXIST;
1651271ab489SXiaojian Du }
1652271ab489SXiaojian Du
1653271ab489SXiaojian Du /* pass data to smu controller */
1654271ab489SXiaojian Du if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1655271ab489SXiaojian Du !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1656271ab489SXiaojian Du ret = smu_cmn_write_watermarks_table(smu);
1657271ab489SXiaojian Du if (ret) {
1658271ab489SXiaojian Du dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1659271ab489SXiaojian Du return ret;
1660271ab489SXiaojian Du }
1661271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_LOADED;
1662271ab489SXiaojian Du }
1663271ab489SXiaojian Du
1664271ab489SXiaojian Du return 0;
1665f46a221bSXiaojian Du }
1666f46a221bSXiaojian Du
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)16670d6516efSLi Ma static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
16680d6516efSLi Ma void **table)
16690d6516efSLi Ma {
16700d6516efSLi Ma struct smu_table_context *smu_table = &smu->smu_table;
16710d6516efSLi Ma struct gpu_metrics_v2_3 *gpu_metrics =
16720d6516efSLi Ma (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
16730d6516efSLi Ma SmuMetrics_legacy_t metrics;
16740d6516efSLi Ma int ret = 0;
16750d6516efSLi Ma
16760d6516efSLi Ma ret = smu_cmn_get_metrics_table(smu, &metrics, true);
16770d6516efSLi Ma if (ret)
16780d6516efSLi Ma return ret;
16790d6516efSLi Ma
16800d6516efSLi Ma smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
16810d6516efSLi Ma
16820d6516efSLi Ma gpu_metrics->temperature_gfx = metrics.GfxTemperature;
16830d6516efSLi Ma gpu_metrics->temperature_soc = metrics.SocTemperature;
16840d6516efSLi Ma memcpy(&gpu_metrics->temperature_core[0],
16850d6516efSLi Ma &metrics.CoreTemperature[0],
16860d6516efSLi Ma sizeof(uint16_t) * 4);
16870d6516efSLi Ma gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
16880d6516efSLi Ma
16890d6516efSLi Ma gpu_metrics->average_gfx_activity = metrics.GfxActivity;
16900d6516efSLi Ma gpu_metrics->average_mm_activity = metrics.UvdActivity;
16910d6516efSLi Ma
16920d6516efSLi Ma gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
16930d6516efSLi Ma gpu_metrics->average_cpu_power = metrics.Power[0];
16940d6516efSLi Ma gpu_metrics->average_soc_power = metrics.Power[1];
16950d6516efSLi Ma gpu_metrics->average_gfx_power = metrics.Power[2];
16960d6516efSLi Ma memcpy(&gpu_metrics->average_core_power[0],
16970d6516efSLi Ma &metrics.CorePower[0],
16980d6516efSLi Ma sizeof(uint16_t) * 4);
16990d6516efSLi Ma
17000d6516efSLi Ma gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
17010d6516efSLi Ma gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
17020d6516efSLi Ma gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
17030d6516efSLi Ma gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
17040d6516efSLi Ma gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
17050d6516efSLi Ma gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
17060d6516efSLi Ma
17070d6516efSLi Ma memcpy(&gpu_metrics->current_coreclk[0],
17080d6516efSLi Ma &metrics.CoreFrequency[0],
17090d6516efSLi Ma sizeof(uint16_t) * 4);
17100d6516efSLi Ma gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
17110d6516efSLi Ma
17120d6516efSLi Ma gpu_metrics->throttle_status = metrics.ThrottlerStatus;
17130d6516efSLi Ma gpu_metrics->indep_throttle_status =
17140d6516efSLi Ma smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
17150d6516efSLi Ma vangogh_throttler_map);
17160d6516efSLi Ma
17170d6516efSLi Ma gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
17180d6516efSLi Ma
17190d6516efSLi Ma *table = (void *)gpu_metrics;
17200d6516efSLi Ma
17210d6516efSLi Ma return sizeof(struct gpu_metrics_v2_3);
17220d6516efSLi Ma }
17230d6516efSLi Ma
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)172486c8236eSXiaojian Du static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
172586c8236eSXiaojian Du void **table)
172686c8236eSXiaojian Du {
172786c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
17287cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics =
17297cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
173086c8236eSXiaojian Du SmuMetrics_legacy_t metrics;
173186c8236eSXiaojian Du int ret = 0;
173286c8236eSXiaojian Du
173386c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true);
173486c8236eSXiaojian Du if (ret)
173586c8236eSXiaojian Du return ret;
173686c8236eSXiaojian Du
17377cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
173886c8236eSXiaojian Du
173986c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.GfxTemperature;
174086c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.SocTemperature;
174186c8236eSXiaojian Du memcpy(&gpu_metrics->temperature_core[0],
174286c8236eSXiaojian Du &metrics.CoreTemperature[0],
174386c8236eSXiaojian Du sizeof(uint16_t) * 4);
174486c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
174586c8236eSXiaojian Du
174686c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.GfxActivity;
174786c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.UvdActivity;
174886c8236eSXiaojian Du
174986c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
175086c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Power[0];
175186c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Power[1];
175286c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Power[2];
175386c8236eSXiaojian Du memcpy(&gpu_metrics->average_core_power[0],
175486c8236eSXiaojian Du &metrics.CorePower[0],
175586c8236eSXiaojian Du sizeof(uint16_t) * 4);
175686c8236eSXiaojian Du
175786c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
175886c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
175986c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
176086c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
176186c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
176286c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
176386c8236eSXiaojian Du
176486c8236eSXiaojian Du memcpy(&gpu_metrics->current_coreclk[0],
176586c8236eSXiaojian Du &metrics.CoreFrequency[0],
176686c8236eSXiaojian Du sizeof(uint16_t) * 4);
176786c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
176886c8236eSXiaojian Du
176986c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.ThrottlerStatus;
17707cab3cffSGraham Sider gpu_metrics->indep_throttle_status =
17717cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
17727cab3cffSGraham Sider vangogh_throttler_map);
177386c8236eSXiaojian Du
177486c8236eSXiaojian Du gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
177586c8236eSXiaojian Du
177686c8236eSXiaojian Du *table = (void *)gpu_metrics;
177786c8236eSXiaojian Du
17787cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2);
177986c8236eSXiaojian Du }
178086c8236eSXiaojian Du
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)17810d6516efSLi Ma static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
17820d6516efSLi Ma void **table)
17830d6516efSLi Ma {
17840d6516efSLi Ma struct smu_table_context *smu_table = &smu->smu_table;
17850d6516efSLi Ma struct gpu_metrics_v2_3 *gpu_metrics =
17860d6516efSLi Ma (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
17870d6516efSLi Ma SmuMetrics_t metrics;
17880d6516efSLi Ma int ret = 0;
17890d6516efSLi Ma
17900d6516efSLi Ma ret = smu_cmn_get_metrics_table(smu, &metrics, true);
17910d6516efSLi Ma if (ret)
17920d6516efSLi Ma return ret;
17930d6516efSLi Ma
17940d6516efSLi Ma smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
17950d6516efSLi Ma
17960d6516efSLi Ma gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
17970d6516efSLi Ma gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
17980d6516efSLi Ma memcpy(&gpu_metrics->temperature_core[0],
17990d6516efSLi Ma &metrics.Current.CoreTemperature[0],
18000d6516efSLi Ma sizeof(uint16_t) * 4);
18010d6516efSLi Ma gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
18020d6516efSLi Ma
18030d6516efSLi Ma gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
18040d6516efSLi Ma gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
18050d6516efSLi Ma memcpy(&gpu_metrics->average_temperature_core[0],
18060d6516efSLi Ma &metrics.Average.CoreTemperature[0],
18070d6516efSLi Ma sizeof(uint16_t) * 4);
18080d6516efSLi Ma gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
18090d6516efSLi Ma
18100d6516efSLi Ma gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
18110d6516efSLi Ma gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
18120d6516efSLi Ma
18130d6516efSLi Ma gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
18140d6516efSLi Ma gpu_metrics->average_cpu_power = metrics.Current.Power[0];
18150d6516efSLi Ma gpu_metrics->average_soc_power = metrics.Current.Power[1];
18160d6516efSLi Ma gpu_metrics->average_gfx_power = metrics.Current.Power[2];
18170d6516efSLi Ma memcpy(&gpu_metrics->average_core_power[0],
18180d6516efSLi Ma &metrics.Average.CorePower[0],
18190d6516efSLi Ma sizeof(uint16_t) * 4);
18200d6516efSLi Ma
18210d6516efSLi Ma gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
18220d6516efSLi Ma gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
18230d6516efSLi Ma gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
18240d6516efSLi Ma gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
18250d6516efSLi Ma gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
18260d6516efSLi Ma gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
18270d6516efSLi Ma
18280d6516efSLi Ma gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
18290d6516efSLi Ma gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
18300d6516efSLi Ma gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
18310d6516efSLi Ma gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
18320d6516efSLi Ma gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
18330d6516efSLi Ma gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
18340d6516efSLi Ma
18350d6516efSLi Ma memcpy(&gpu_metrics->current_coreclk[0],
18360d6516efSLi Ma &metrics.Current.CoreFrequency[0],
18370d6516efSLi Ma sizeof(uint16_t) * 4);
18380d6516efSLi Ma gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
18390d6516efSLi Ma
18400d6516efSLi Ma gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
18410d6516efSLi Ma gpu_metrics->indep_throttle_status =
18420d6516efSLi Ma smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
18430d6516efSLi Ma vangogh_throttler_map);
18440d6516efSLi Ma
18450d6516efSLi Ma gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
18460d6516efSLi Ma
18470d6516efSLi Ma *table = (void *)gpu_metrics;
18480d6516efSLi Ma
18490d6516efSLi Ma return sizeof(struct gpu_metrics_v2_3);
18500d6516efSLi Ma }
18510d6516efSLi Ma
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)185241cec40bSWenyou Yang static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
185341cec40bSWenyou Yang void **table)
185441cec40bSWenyou Yang {
185541cec40bSWenyou Yang SmuMetrics_t metrics;
185641cec40bSWenyou Yang struct smu_table_context *smu_table = &smu->smu_table;
185741cec40bSWenyou Yang struct gpu_metrics_v2_4 *gpu_metrics =
185841cec40bSWenyou Yang (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
185941cec40bSWenyou Yang int ret = 0;
186041cec40bSWenyou Yang
186141cec40bSWenyou Yang ret = smu_cmn_get_metrics_table(smu, &metrics, true);
186241cec40bSWenyou Yang if (ret)
186341cec40bSWenyou Yang return ret;
186441cec40bSWenyou Yang
186541cec40bSWenyou Yang smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
186641cec40bSWenyou Yang
186741cec40bSWenyou Yang gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
186841cec40bSWenyou Yang gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
186941cec40bSWenyou Yang memcpy(&gpu_metrics->temperature_core[0],
187041cec40bSWenyou Yang &metrics.Current.CoreTemperature[0],
187141cec40bSWenyou Yang sizeof(uint16_t) * 4);
187241cec40bSWenyou Yang gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
187341cec40bSWenyou Yang
187441cec40bSWenyou Yang gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
187541cec40bSWenyou Yang gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
187641cec40bSWenyou Yang memcpy(&gpu_metrics->average_temperature_core[0],
187741cec40bSWenyou Yang &metrics.Average.CoreTemperature[0],
187841cec40bSWenyou Yang sizeof(uint16_t) * 4);
187941cec40bSWenyou Yang gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
188041cec40bSWenyou Yang
1881102b80f6SKun Liu gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1882102b80f6SKun Liu gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
188341cec40bSWenyou Yang
1884102b80f6SKun Liu gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1885102b80f6SKun Liu gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1886102b80f6SKun Liu gpu_metrics->average_soc_power = metrics.Average.Power[1];
1887102b80f6SKun Liu gpu_metrics->average_gfx_power = metrics.Average.Power[2];
188841cec40bSWenyou Yang
1889102b80f6SKun Liu gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1890102b80f6SKun Liu gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1891102b80f6SKun Liu gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
189241cec40bSWenyou Yang
1893102b80f6SKun Liu gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1894102b80f6SKun Liu gpu_metrics->average_soc_current = metrics.Average.Current[1];
1895102b80f6SKun Liu gpu_metrics->average_gfx_current = metrics.Average.Current[2];
189641cec40bSWenyou Yang
189741cec40bSWenyou Yang memcpy(&gpu_metrics->average_core_power[0],
189841cec40bSWenyou Yang &metrics.Average.CorePower[0],
189941cec40bSWenyou Yang sizeof(uint16_t) * 4);
190041cec40bSWenyou Yang
190141cec40bSWenyou Yang gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
190241cec40bSWenyou Yang gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
190341cec40bSWenyou Yang gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
190441cec40bSWenyou Yang gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
190541cec40bSWenyou Yang gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
190641cec40bSWenyou Yang gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
190741cec40bSWenyou Yang
190841cec40bSWenyou Yang gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
190941cec40bSWenyou Yang gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
191041cec40bSWenyou Yang gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
191141cec40bSWenyou Yang gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
191241cec40bSWenyou Yang gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
191341cec40bSWenyou Yang gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
191441cec40bSWenyou Yang
191541cec40bSWenyou Yang memcpy(&gpu_metrics->current_coreclk[0],
191641cec40bSWenyou Yang &metrics.Current.CoreFrequency[0],
191741cec40bSWenyou Yang sizeof(uint16_t) * 4);
191841cec40bSWenyou Yang gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
191941cec40bSWenyou Yang
192041cec40bSWenyou Yang gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
192141cec40bSWenyou Yang gpu_metrics->indep_throttle_status =
192241cec40bSWenyou Yang smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
192341cec40bSWenyou Yang vangogh_throttler_map);
192441cec40bSWenyou Yang
192541cec40bSWenyou Yang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
192641cec40bSWenyou Yang
192741cec40bSWenyou Yang *table = (void *)gpu_metrics;
192841cec40bSWenyou Yang
192941cec40bSWenyou Yang return sizeof(struct gpu_metrics_v2_4);
193041cec40bSWenyou Yang }
193141cec40bSWenyou Yang
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1932fd253334SXiaojian Du static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1933fd253334SXiaojian Du void **table)
1934fd253334SXiaojian Du {
1935fd253334SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
19367cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics =
19377cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1938fd253334SXiaojian Du SmuMetrics_t metrics;
1939fd253334SXiaojian Du int ret = 0;
1940fd253334SXiaojian Du
1941fd253334SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1942fd253334SXiaojian Du if (ret)
1943fd253334SXiaojian Du return ret;
1944fd253334SXiaojian Du
19457cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1946fd253334SXiaojian Du
194786c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
194886c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1949fd253334SXiaojian Du memcpy(&gpu_metrics->temperature_core[0],
195086c8236eSXiaojian Du &metrics.Current.CoreTemperature[0],
195186c8236eSXiaojian Du sizeof(uint16_t) * 4);
195286c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1953fd253334SXiaojian Du
195486c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
195586c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1956fd253334SXiaojian Du
195786c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
195886c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Current.Power[0];
195986c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Current.Power[1];
196086c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1961fd253334SXiaojian Du memcpy(&gpu_metrics->average_core_power[0],
196286c8236eSXiaojian Du &metrics.Average.CorePower[0],
196386c8236eSXiaojian Du sizeof(uint16_t) * 4);
1964fd253334SXiaojian Du
196586c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
196686c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
196786c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
196886c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
196986c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
197086c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
197186c8236eSXiaojian Du
197286c8236eSXiaojian Du gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
197386c8236eSXiaojian Du gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
197486c8236eSXiaojian Du gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
197586c8236eSXiaojian Du gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
197686c8236eSXiaojian Du gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
197786c8236eSXiaojian Du gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1978fd253334SXiaojian Du
1979fd253334SXiaojian Du memcpy(&gpu_metrics->current_coreclk[0],
198086c8236eSXiaojian Du &metrics.Current.CoreFrequency[0],
198186c8236eSXiaojian Du sizeof(uint16_t) * 4);
198286c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1983fd253334SXiaojian Du
198486c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
19857cab3cffSGraham Sider gpu_metrics->indep_throttle_status =
19867cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
19877cab3cffSGraham Sider vangogh_throttler_map);
1988fd253334SXiaojian Du
1989de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1990de4b7cd8SKevin Wang
1991fd253334SXiaojian Du *table = (void *)gpu_metrics;
1992fd253334SXiaojian Du
19937cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2);
1994fd253334SXiaojian Du }
1995fd253334SXiaojian Du
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)199686c8236eSXiaojian Du static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
199786c8236eSXiaojian Du void **table)
199886c8236eSXiaojian Du {
199941cec40bSWenyou Yang uint32_t smu_program;
200041cec40bSWenyou Yang uint32_t fw_version;
200186c8236eSXiaojian Du int ret = 0;
200286c8236eSXiaojian Du
2003710d9caeSYifan Zhang smu_program = (smu->smc_fw_version >> 24) & 0xff;
2004710d9caeSYifan Zhang fw_version = smu->smc_fw_version & 0xffffff;
200541cec40bSWenyou Yang if (smu_program == 6) {
200641cec40bSWenyou Yang if (fw_version >= 0x3F0800)
200741cec40bSWenyou Yang ret = vangogh_get_gpu_metrics_v2_4(smu, table);
200841cec40bSWenyou Yang else
200941cec40bSWenyou Yang ret = vangogh_get_gpu_metrics_v2_3(smu, table);
201041cec40bSWenyou Yang
201141cec40bSWenyou Yang } else {
2012710d9caeSYifan Zhang if (smu->smc_fw_version >= 0x043F3E00) {
2013710d9caeSYifan Zhang if (smu->smc_fw_if_version < 0x3)
20140d6516efSLi Ma ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
20150d6516efSLi Ma else
20160d6516efSLi Ma ret = vangogh_get_gpu_metrics_v2_3(smu, table);
20170d6516efSLi Ma } else {
2018710d9caeSYifan Zhang if (smu->smc_fw_if_version < 0x3)
201986c8236eSXiaojian Du ret = vangogh_get_legacy_gpu_metrics(smu, table);
202086c8236eSXiaojian Du else
202186c8236eSXiaojian Du ret = vangogh_get_gpu_metrics(smu, table);
20220d6516efSLi Ma }
202341cec40bSWenyou Yang }
202486c8236eSXiaojian Du
202586c8236eSXiaojian Du return ret;
202686c8236eSXiaojian Du }
202786c8236eSXiaojian Du
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2028c98ee897SXiaojian Du static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2029c98ee897SXiaojian Du long input[], uint32_t size)
2030c98ee897SXiaojian Du {
2031c98ee897SXiaojian Du int ret = 0;
2032d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2033c98ee897SXiaojian Du
2034d7379efaSXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2035d7ef887fSXiaojian Du dev_warn(smu->adev->dev,
2036ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2037c98ee897SXiaojian Du return -EINVAL;
2038c98ee897SXiaojian Du }
2039c98ee897SXiaojian Du
2040c98ee897SXiaojian Du switch (type) {
20410d90d0ddSHuang Rui case PP_OD_EDIT_CCLK_VDDC_TABLE:
20420d90d0ddSHuang Rui if (size != 3) {
20430d90d0ddSHuang Rui dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
20440d90d0ddSHuang Rui return -EINVAL;
20450d90d0ddSHuang Rui }
20464aef0ebcSHuang Rui if (input[0] >= smu->cpu_core_num) {
20470d90d0ddSHuang Rui dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
20484aef0ebcSHuang Rui smu->cpu_core_num);
20490d90d0ddSHuang Rui }
20500d90d0ddSHuang Rui smu->cpu_core_id_select = input[0];
20510d90d0ddSHuang Rui if (input[1] == 0) {
20520d90d0ddSHuang Rui if (input[2] < smu->cpu_default_soft_min_freq) {
20530d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
20540d90d0ddSHuang Rui input[2], smu->cpu_default_soft_min_freq);
20550d90d0ddSHuang Rui return -EINVAL;
20560d90d0ddSHuang Rui }
20570d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = input[2];
20580d90d0ddSHuang Rui } else if (input[1] == 1) {
20590d90d0ddSHuang Rui if (input[2] > smu->cpu_default_soft_max_freq) {
20600d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
20610d90d0ddSHuang Rui input[2], smu->cpu_default_soft_max_freq);
20620d90d0ddSHuang Rui return -EINVAL;
20630d90d0ddSHuang Rui }
20640d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = input[2];
20650d90d0ddSHuang Rui } else {
20660d90d0ddSHuang Rui return -EINVAL;
20670d90d0ddSHuang Rui }
20680d90d0ddSHuang Rui break;
2069c98ee897SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE:
2070c98ee897SXiaojian Du if (size != 2) {
2071c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2072c98ee897SXiaojian Du return -EINVAL;
2073c98ee897SXiaojian Du }
2074c98ee897SXiaojian Du
2075c98ee897SXiaojian Du if (input[0] == 0) {
2076c98ee897SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) {
2077307f049bSXiaojian Du dev_warn(smu->adev->dev,
2078307f049bSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2079c98ee897SXiaojian Du input[1], smu->gfx_default_hard_min_freq);
2080c98ee897SXiaojian Du return -EINVAL;
2081c98ee897SXiaojian Du }
2082c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = input[1];
2083c98ee897SXiaojian Du } else if (input[0] == 1) {
2084c98ee897SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) {
2085307f049bSXiaojian Du dev_warn(smu->adev->dev,
2086307f049bSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2087c98ee897SXiaojian Du input[1], smu->gfx_default_soft_max_freq);
2088c98ee897SXiaojian Du return -EINVAL;
2089c98ee897SXiaojian Du }
2090c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = input[1];
2091c98ee897SXiaojian Du } else {
2092c98ee897SXiaojian Du return -EINVAL;
2093c98ee897SXiaojian Du }
2094c98ee897SXiaojian Du break;
2095c98ee897SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE:
2096c98ee897SXiaojian Du if (size != 0) {
2097c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2098c98ee897SXiaojian Du return -EINVAL;
2099c98ee897SXiaojian Du } else {
2100c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2101c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
21020d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
21030d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2104c98ee897SXiaojian Du }
2105c98ee897SXiaojian Du break;
2106c98ee897SXiaojian Du case PP_OD_COMMIT_DPM_TABLE:
2107c98ee897SXiaojian Du if (size != 0) {
2108c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2109c98ee897SXiaojian Du return -EINVAL;
2110c98ee897SXiaojian Du } else {
2111c98ee897SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2112307f049bSXiaojian Du dev_err(smu->adev->dev,
2113f5d8e164SColin Ian King "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2114307f049bSXiaojian Du smu->gfx_actual_hard_min_freq,
2115307f049bSXiaojian Du smu->gfx_actual_soft_max_freq);
2116c98ee897SXiaojian Du return -EINVAL;
2117c98ee897SXiaojian Du }
2118c98ee897SXiaojian Du
2119c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2120c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq, NULL);
2121c98ee897SXiaojian Du if (ret) {
2122c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!");
2123c98ee897SXiaojian Du return ret;
2124c98ee897SXiaojian Du }
2125c98ee897SXiaojian Du
2126c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2127c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq, NULL);
2128c98ee897SXiaojian Du if (ret) {
2129c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!");
2130c98ee897SXiaojian Du return ret;
2131c98ee897SXiaojian Du }
21320d90d0ddSHuang Rui
21330d90d0ddSHuang Rui if (smu->adev->pm.fw_version < 0x43f1b00) {
21340d90d0ddSHuang Rui dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
21350d90d0ddSHuang Rui break;
21360d90d0ddSHuang Rui }
21370d90d0ddSHuang Rui
21380d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
21390d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20)
21400d90d0ddSHuang Rui | smu->cpu_actual_soft_min_freq),
21410d90d0ddSHuang Rui NULL);
21420d90d0ddSHuang Rui if (ret) {
21430d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set hard min cclk failed!");
21440d90d0ddSHuang Rui return ret;
21450d90d0ddSHuang Rui }
21460d90d0ddSHuang Rui
21470d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
21480d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20)
21490d90d0ddSHuang Rui | smu->cpu_actual_soft_max_freq),
21500d90d0ddSHuang Rui NULL);
21510d90d0ddSHuang Rui if (ret) {
21520d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set soft max cclk failed!");
21530d90d0ddSHuang Rui return ret;
21540d90d0ddSHuang Rui }
2155c98ee897SXiaojian Du }
2156c98ee897SXiaojian Du break;
2157c98ee897SXiaojian Du default:
2158c98ee897SXiaojian Du return -ENOSYS;
2159c98ee897SXiaojian Du }
2160c98ee897SXiaojian Du
2161c98ee897SXiaojian Du return ret;
2162c98ee897SXiaojian Du }
2163c98ee897SXiaojian Du
vangogh_set_default_dpm_tables(struct smu_context * smu)2164fce8a4acSJinzhou Su static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2165c98ee897SXiaojian Du {
2166c98ee897SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
2167c98ee897SXiaojian Du
2168c98ee897SXiaojian Du return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2169c98ee897SXiaojian Du }
2170c98ee897SXiaojian Du
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2171c98ee897SXiaojian Du static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2172c98ee897SXiaojian Du {
2173c98ee897SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2174c98ee897SXiaojian Du
2175c98ee897SXiaojian Du smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2176c98ee897SXiaojian Du smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2177c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = 0;
2178c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = 0;
2179c98ee897SXiaojian Du
21800d90d0ddSHuang Rui smu->cpu_default_soft_min_freq = 1400;
21810d90d0ddSHuang Rui smu->cpu_default_soft_max_freq = 3500;
21820d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = 0;
21830d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = 0;
21840d90d0ddSHuang Rui
2185c98ee897SXiaojian Du return 0;
2186c98ee897SXiaojian Du }
2187c98ee897SXiaojian Du
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2188ae7b32e7SXiaojian Du static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2189ae7b32e7SXiaojian Du {
2190ae7b32e7SXiaojian Du DpmClocks_t *table = smu->smu_table.clocks_table;
2191ae7b32e7SXiaojian Du int i;
2192ae7b32e7SXiaojian Du
2193ae7b32e7SXiaojian Du if (!clock_table || !table)
2194ae7b32e7SXiaojian Du return -EINVAL;
2195ae7b32e7SXiaojian Du
2196ae7b32e7SXiaojian Du for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2197ae7b32e7SXiaojian Du clock_table->SocClocks[i].Freq = table->SocClocks[i];
2198ae7b32e7SXiaojian Du clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2199ae7b32e7SXiaojian Du }
2200ae7b32e7SXiaojian Du
2201ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2202ae7b32e7SXiaojian Du clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2203ae7b32e7SXiaojian Du clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2204ae7b32e7SXiaojian Du }
2205ae7b32e7SXiaojian Du
2206ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2207ae7b32e7SXiaojian Du clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2208ae7b32e7SXiaojian Du clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2209ae7b32e7SXiaojian Du }
2210ae7b32e7SXiaojian Du
2211ae7b32e7SXiaojian Du return 0;
2212ae7b32e7SXiaojian Du }
2213ae7b32e7SXiaojian Du
vangogh_notify_rlc_state(struct smu_context * smu,bool en)22148c4e9105SPerry Yuan static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2215a0f55287SXiaomeng Hou {
22169e3a6ab7SXiaomeng Hou struct amdgpu_device *adev = smu->adev;
2217aedebd40SHuang Rui int ret = 0;
22189e3a6ab7SXiaomeng Hou
22195b2e2c09SAlex Deucher if (adev->pm.fw_version >= 0x43f1700 && !en)
2220aedebd40SHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
22215b2e2c09SAlex Deucher RLC_STATUS_OFF, NULL);
2222aedebd40SHuang Rui
2223aedebd40SHuang Rui return ret;
2224a0f55287SXiaomeng Hou }
2225a0f55287SXiaomeng Hou
vangogh_post_smu_init(struct smu_context * smu)2226eefdf047SJinzhou Su static int vangogh_post_smu_init(struct smu_context *smu)
2227eefdf047SJinzhou Su {
2228eefdf047SJinzhou Su struct amdgpu_device *adev = smu->adev;
2229eefdf047SJinzhou Su uint32_t tmp;
22303313ef18SJinzhou Su int ret = 0;
2231eefdf047SJinzhou Su uint8_t aon_bits = 0;
2232eefdf047SJinzhou Su /* Two CUs in one WGP */
2233eefdf047SJinzhou Su uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2234eefdf047SJinzhou Su uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2235eefdf047SJinzhou Su adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2236eefdf047SJinzhou Su
22373313ef18SJinzhou Su /* allow message will be sent after enable message on Vangogh*/
22387ade3ca9SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2239bb377febSJinzhou Su (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
22403313ef18SJinzhou Su ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
22413313ef18SJinzhou Su if (ret) {
22423313ef18SJinzhou Su dev_err(adev->dev, "Failed to Enable GfxOff!\n");
22433313ef18SJinzhou Su return ret;
22443313ef18SJinzhou Su }
2245bb377febSJinzhou Su } else {
2246bb377febSJinzhou Su adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2247bb377febSJinzhou Su dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2248bb377febSJinzhou Su }
22493313ef18SJinzhou Su
2250eefdf047SJinzhou Su /* if all CUs are active, no need to power off any WGPs */
2251eefdf047SJinzhou Su if (total_cu == adev->gfx.cu_info.number)
2252eefdf047SJinzhou Su return 0;
2253eefdf047SJinzhou Su
2254eefdf047SJinzhou Su /*
2255eefdf047SJinzhou Su * Calculate the total bits number of always on WGPs for all SA/SEs in
2256eefdf047SJinzhou Su * RLC_PG_ALWAYS_ON_WGP_MASK.
2257eefdf047SJinzhou Su */
2258eefdf047SJinzhou Su tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2259eefdf047SJinzhou Su tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2260eefdf047SJinzhou Su
2261eefdf047SJinzhou Su aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2262eefdf047SJinzhou Su
2263eefdf047SJinzhou Su /* Do not request any WGPs less than set in the AON_WGP_MASK */
2264eefdf047SJinzhou Su if (aon_bits > req_active_wgps) {
2265eefdf047SJinzhou Su dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2266eefdf047SJinzhou Su return 0;
2267eefdf047SJinzhou Su } else {
2268eefdf047SJinzhou Su return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2269eefdf047SJinzhou Su }
2270eefdf047SJinzhou Su }
2271eefdf047SJinzhou Su
vangogh_mode_reset(struct smu_context * smu,int type)227274353883SHuang Rui static int vangogh_mode_reset(struct smu_context *smu, int type)
227374353883SHuang Rui {
227474353883SHuang Rui int ret = 0, index = 0;
227574353883SHuang Rui
227674353883SHuang Rui index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
227774353883SHuang Rui SMU_MSG_GfxDeviceDriverReset);
227874353883SHuang Rui if (index < 0)
227974353883SHuang Rui return index == -EACCES ? 0 : index;
228074353883SHuang Rui
228174353883SHuang Rui mutex_lock(&smu->message_lock);
228274353883SHuang Rui
228374353883SHuang Rui ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
228474353883SHuang Rui
228574353883SHuang Rui mutex_unlock(&smu->message_lock);
228674353883SHuang Rui
228774353883SHuang Rui mdelay(10);
228874353883SHuang Rui
228974353883SHuang Rui return ret;
229074353883SHuang Rui }
229174353883SHuang Rui
vangogh_mode2_reset(struct smu_context * smu)229220e157c7SAlex Deucher static int vangogh_mode2_reset(struct smu_context *smu)
229320e157c7SAlex Deucher {
229474353883SHuang Rui return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
229520e157c7SAlex Deucher }
229620e157c7SAlex Deucher
229743195162SAndré Almeida /**
229843195162SAndré Almeida * vangogh_get_gfxoff_status - Get gfxoff status
229943195162SAndré Almeida *
230043195162SAndré Almeida * @smu: amdgpu_device pointer
230143195162SAndré Almeida *
230243195162SAndré Almeida * Get current gfxoff status
230343195162SAndré Almeida *
230443195162SAndré Almeida * Return:
230543195162SAndré Almeida * * 0 - GFXOFF (default if enabled).
230643195162SAndré Almeida * * 1 - Transition out of GFX State.
230743195162SAndré Almeida * * 2 - Not in GFXOFF.
230843195162SAndré Almeida * * 3 - Transition into GFXOFF.
230943195162SAndré Almeida */
vangogh_get_gfxoff_status(struct smu_context * smu)231043195162SAndré Almeida static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
231143195162SAndré Almeida {
231243195162SAndré Almeida struct amdgpu_device *adev = smu->adev;
231343195162SAndré Almeida u32 reg, gfxoff_status;
231443195162SAndré Almeida
231543195162SAndré Almeida reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
231643195162SAndré Almeida gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
231743195162SAndré Almeida >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
231843195162SAndré Almeida
231943195162SAndré Almeida return gfxoff_status;
232043195162SAndré Almeida }
232143195162SAndré Almeida
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2322488f211dSEvan Quan static int vangogh_get_power_limit(struct smu_context *smu,
2323488f211dSEvan Quan uint32_t *current_power_limit,
2324488f211dSEvan Quan uint32_t *default_power_limit,
232519589468SMa Jun uint32_t *max_power_limit,
232619589468SMa Jun uint32_t *min_power_limit)
2327ae07970aSXiaomeng Hou {
2328ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2329ae07970aSXiaomeng Hou smu->smu_power.power_context;
2330ae07970aSXiaomeng Hou uint32_t ppt_limit;
2331ae07970aSXiaomeng Hou int ret = 0;
2332ae07970aSXiaomeng Hou
2333ae07970aSXiaomeng Hou if (smu->adev->pm.fw_version < 0x43f1e00)
2334ae07970aSXiaomeng Hou return ret;
2335ae07970aSXiaomeng Hou
2336ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2337ae07970aSXiaomeng Hou if (ret) {
2338ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2339ae07970aSXiaomeng Hou return ret;
2340ae07970aSXiaomeng Hou }
2341ae07970aSXiaomeng Hou /* convert from milliwatt to watt */
2342488f211dSEvan Quan if (current_power_limit)
2343488f211dSEvan Quan *current_power_limit = ppt_limit / 1000;
2344488f211dSEvan Quan if (default_power_limit)
2345488f211dSEvan Quan *default_power_limit = ppt_limit / 1000;
2346488f211dSEvan Quan if (max_power_limit)
2347488f211dSEvan Quan *max_power_limit = 29;
234819589468SMa Jun if (min_power_limit)
234919589468SMa Jun *min_power_limit = 0;
2350ae07970aSXiaomeng Hou
2351ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2352ae07970aSXiaomeng Hou if (ret) {
2353ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2354ae07970aSXiaomeng Hou return ret;
2355ae07970aSXiaomeng Hou }
2356ae07970aSXiaomeng Hou /* convert from milliwatt to watt */
23576e58941cSEric Huang power_context->current_fast_ppt_limit =
23586e58941cSEric Huang power_context->default_fast_ppt_limit = ppt_limit / 1000;
2359ae07970aSXiaomeng Hou power_context->max_fast_ppt_limit = 30;
2360ae07970aSXiaomeng Hou
2361ae07970aSXiaomeng Hou return ret;
2362ae07970aSXiaomeng Hou }
2363ae07970aSXiaomeng Hou
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2364ae07970aSXiaomeng Hou static int vangogh_get_ppt_limit(struct smu_context *smu,
2365ae07970aSXiaomeng Hou uint32_t *ppt_limit,
2366ae07970aSXiaomeng Hou enum smu_ppt_limit_type type,
2367ae07970aSXiaomeng Hou enum smu_ppt_limit_level level)
2368ae07970aSXiaomeng Hou {
2369ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2370ae07970aSXiaomeng Hou smu->smu_power.power_context;
2371ae07970aSXiaomeng Hou
2372ae07970aSXiaomeng Hou if (!power_context)
2373ae07970aSXiaomeng Hou return -EOPNOTSUPP;
2374ae07970aSXiaomeng Hou
2375ae07970aSXiaomeng Hou if (type == SMU_FAST_PPT_LIMIT) {
2376ae07970aSXiaomeng Hou switch (level) {
2377ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_MAX:
2378ae07970aSXiaomeng Hou *ppt_limit = power_context->max_fast_ppt_limit;
2379ae07970aSXiaomeng Hou break;
2380ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_CURRENT:
2381ae07970aSXiaomeng Hou *ppt_limit = power_context->current_fast_ppt_limit;
2382ae07970aSXiaomeng Hou break;
23836e58941cSEric Huang case SMU_PPT_LIMIT_DEFAULT:
23846e58941cSEric Huang *ppt_limit = power_context->default_fast_ppt_limit;
23856e58941cSEric Huang break;
2386ae07970aSXiaomeng Hou default:
2387ae07970aSXiaomeng Hou break;
2388ae07970aSXiaomeng Hou }
2389ae07970aSXiaomeng Hou }
2390ae07970aSXiaomeng Hou
2391ae07970aSXiaomeng Hou return 0;
2392ae07970aSXiaomeng Hou }
2393ae07970aSXiaomeng Hou
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)23942d1ac1cbSDarren Powell static int vangogh_set_power_limit(struct smu_context *smu,
23952d1ac1cbSDarren Powell enum smu_ppt_limit_type limit_type,
23962d1ac1cbSDarren Powell uint32_t ppt_limit)
2397ae07970aSXiaomeng Hou {
2398ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2399ae07970aSXiaomeng Hou smu->smu_power.power_context;
2400ae07970aSXiaomeng Hou int ret = 0;
2401ae07970aSXiaomeng Hou
2402ae07970aSXiaomeng Hou if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2403ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2404ae07970aSXiaomeng Hou return -EOPNOTSUPP;
2405ae07970aSXiaomeng Hou }
2406ae07970aSXiaomeng Hou
2407ae07970aSXiaomeng Hou switch (limit_type) {
2408ae07970aSXiaomeng Hou case SMU_DEFAULT_PPT_LIMIT:
2409ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu,
2410ae07970aSXiaomeng Hou SMU_MSG_SetSlowPPTLimit,
2411ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */
2412ae07970aSXiaomeng Hou NULL);
2413ae07970aSXiaomeng Hou if (ret)
2414ae07970aSXiaomeng Hou return ret;
2415ae07970aSXiaomeng Hou
2416ae07970aSXiaomeng Hou smu->current_power_limit = ppt_limit;
2417ae07970aSXiaomeng Hou break;
2418ae07970aSXiaomeng Hou case SMU_FAST_PPT_LIMIT:
2419ae07970aSXiaomeng Hou ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2420ae07970aSXiaomeng Hou if (ppt_limit > power_context->max_fast_ppt_limit) {
2421ae07970aSXiaomeng Hou dev_err(smu->adev->dev,
2422ae07970aSXiaomeng Hou "New power limit (%d) is over the max allowed %d\n",
2423ae07970aSXiaomeng Hou ppt_limit, power_context->max_fast_ppt_limit);
2424ae07970aSXiaomeng Hou return ret;
2425ae07970aSXiaomeng Hou }
2426ae07970aSXiaomeng Hou
2427ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu,
2428ae07970aSXiaomeng Hou SMU_MSG_SetFastPPTLimit,
2429ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */
2430ae07970aSXiaomeng Hou NULL);
2431ae07970aSXiaomeng Hou if (ret)
2432ae07970aSXiaomeng Hou return ret;
2433ae07970aSXiaomeng Hou
2434ae07970aSXiaomeng Hou power_context->current_fast_ppt_limit = ppt_limit;
2435ae07970aSXiaomeng Hou break;
2436ae07970aSXiaomeng Hou default:
2437ae07970aSXiaomeng Hou return -EINVAL;
2438ae07970aSXiaomeng Hou }
2439ae07970aSXiaomeng Hou
2440ae07970aSXiaomeng Hou return ret;
2441ae07970aSXiaomeng Hou }
2442ae07970aSXiaomeng Hou
24431ed5a845SAndré Almeida /**
24441ed5a845SAndré Almeida * vangogh_set_gfxoff_residency
24451ed5a845SAndré Almeida *
24461ed5a845SAndré Almeida * @smu: amdgpu_device pointer
24471ed5a845SAndré Almeida * @start: start/stop residency log
24481ed5a845SAndré Almeida *
24491ed5a845SAndré Almeida * This function will be used to log gfxoff residency
24501ed5a845SAndré Almeida *
24511ed5a845SAndré Almeida *
24521ed5a845SAndré Almeida * Returns standard response codes.
24531ed5a845SAndré Almeida */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)24541ed5a845SAndré Almeida static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
24551ed5a845SAndré Almeida {
24561ed5a845SAndré Almeida int ret = 0;
24571ed5a845SAndré Almeida u32 residency;
24581ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
24591ed5a845SAndré Almeida
24601ed5a845SAndré Almeida if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
24611ed5a845SAndré Almeida return 0;
24621ed5a845SAndré Almeida
24631ed5a845SAndré Almeida ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
24641ed5a845SAndré Almeida start, &residency);
2465*b2871de6STim Huang if (ret)
2466*b2871de6STim Huang return ret;
24671ed5a845SAndré Almeida
24681ed5a845SAndré Almeida if (!start)
24691ed5a845SAndré Almeida adev->gfx.gfx_off_residency = residency;
24701ed5a845SAndré Almeida
24711ed5a845SAndré Almeida return ret;
24721ed5a845SAndré Almeida }
24731ed5a845SAndré Almeida
24741ed5a845SAndré Almeida /**
24751ed5a845SAndré Almeida * vangogh_get_gfxoff_residency
24761ed5a845SAndré Almeida *
24771ed5a845SAndré Almeida * @smu: amdgpu_device pointer
247863d99a34SLee Jones * @residency: placeholder for return value
24791ed5a845SAndré Almeida *
24801ed5a845SAndré Almeida * This function will be used to get gfxoff residency.
24811ed5a845SAndré Almeida *
24821ed5a845SAndré Almeida * Returns standard response codes.
24831ed5a845SAndré Almeida */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)24841ed5a845SAndré Almeida static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
24851ed5a845SAndré Almeida {
24861ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
24871ed5a845SAndré Almeida
24881ed5a845SAndré Almeida *residency = adev->gfx.gfx_off_residency;
24891ed5a845SAndré Almeida
24901ed5a845SAndré Almeida return 0;
24911ed5a845SAndré Almeida }
24921ed5a845SAndré Almeida
24931ed5a845SAndré Almeida /**
24941ed5a845SAndré Almeida * vangogh_get_gfxoff_entrycount - get gfxoff entry count
24951ed5a845SAndré Almeida *
24961ed5a845SAndré Almeida * @smu: amdgpu_device pointer
249763d99a34SLee Jones * @entrycount: placeholder for return value
24981ed5a845SAndré Almeida *
24991ed5a845SAndré Almeida * This function will be used to get gfxoff entry count
25001ed5a845SAndré Almeida *
25011ed5a845SAndré Almeida * Returns standard response codes.
25021ed5a845SAndré Almeida */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)25031ed5a845SAndré Almeida static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
25041ed5a845SAndré Almeida {
25051ed5a845SAndré Almeida int ret = 0, value = 0;
25061ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
25071ed5a845SAndré Almeida
25081ed5a845SAndré Almeida if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
25091ed5a845SAndré Almeida return 0;
25101ed5a845SAndré Almeida
25111ed5a845SAndré Almeida ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
25121ed5a845SAndré Almeida *entrycount = value + adev->gfx.gfx_off_entrycount;
25131ed5a845SAndré Almeida
25141ed5a845SAndré Almeida return ret;
25151ed5a845SAndré Almeida }
25161ed5a845SAndré Almeida
2517f46a221bSXiaojian Du static const struct pptable_funcs vangogh_ppt_funcs = {
2518271ab489SXiaojian Du
2519f46a221bSXiaojian Du .check_fw_status = smu_v11_0_check_fw_status,
2520f46a221bSXiaojian Du .check_fw_version = smu_v11_0_check_fw_version,
2521f46a221bSXiaojian Du .init_smc_tables = vangogh_init_smc_tables,
2522f46a221bSXiaojian Du .fini_smc_tables = smu_v11_0_fini_smc_tables,
2523f46a221bSXiaojian Du .init_power = smu_v11_0_init_power,
2524f46a221bSXiaojian Du .fini_power = smu_v11_0_fini_power,
2525f46a221bSXiaojian Du .register_irq_handler = smu_v11_0_register_irq_handler,
2526f46a221bSXiaojian Du .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2527f46a221bSXiaojian Du .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2528f46a221bSXiaojian Du .send_smc_msg = smu_cmn_send_smc_msg,
2529271ab489SXiaojian Du .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2530271ab489SXiaojian Du .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2531f46a221bSXiaojian Du .is_dpm_running = vangogh_is_dpm_running,
2532271ab489SXiaojian Du .read_sensor = vangogh_read_sensor,
25330c3c9936SKun Liu .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
25340c3c9936SKun Liu .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
25355af779adSEvan Quan .get_enabled_mask = smu_cmn_get_enabled_mask,
2536f46a221bSXiaojian Du .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2537271ab489SXiaojian Du .set_watermarks_table = vangogh_set_watermarks_table,
2538271ab489SXiaojian Du .set_driver_table_location = smu_v11_0_set_driver_table_location,
2539f46a221bSXiaojian Du .interrupt_work = smu_v11_0_interrupt_work,
254086c8236eSXiaojian Du .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2541c98ee897SXiaojian Du .od_edit_dpm_table = vangogh_od_edit_dpm_table,
254286c8236eSXiaojian Du .print_clk_levels = vangogh_common_print_clk_levels,
2543c98ee897SXiaojian Du .set_default_dpm_table = vangogh_set_default_dpm_tables,
2544c98ee897SXiaojian Du .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
25458c4e9105SPerry Yuan .notify_rlc_state = vangogh_notify_rlc_state,
2546d0e4e112SXiaojian Du .feature_is_enabled = smu_cmn_feature_is_enabled,
2547d0e4e112SXiaojian Du .set_power_profile_mode = vangogh_set_power_profile_mode,
2548307f049bSXiaojian Du .get_power_profile_mode = vangogh_get_power_profile_mode,
2549ae7b32e7SXiaojian Du .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2550dd9e0b21SXiaojian Du .force_clk_levels = vangogh_force_clk_levels,
2551ea173d15SXiaojian Du .set_performance_level = vangogh_set_performance_level,
2552eefdf047SJinzhou Su .post_init = vangogh_post_smu_init,
255320e157c7SAlex Deucher .mode2_reset = vangogh_mode2_reset,
2554b58ce1feSJinzhou Su .gfx_off_control = smu_v11_0_gfx_off_control,
255543195162SAndré Almeida .get_gfx_off_status = vangogh_get_gfxoff_status,
25561ed5a845SAndré Almeida .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
25571ed5a845SAndré Almeida .get_gfx_off_residency = vangogh_get_gfxoff_residency,
25581ed5a845SAndré Almeida .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2559ae07970aSXiaomeng Hou .get_ppt_limit = vangogh_get_ppt_limit,
2560ae07970aSXiaomeng Hou .get_power_limit = vangogh_get_power_limit,
2561ae07970aSXiaomeng Hou .set_power_limit = vangogh_set_power_limit,
25623495d3c3SXiaojian Du .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2563f46a221bSXiaojian Du };
2564f46a221bSXiaojian Du
vangogh_set_ppt_funcs(struct smu_context * smu)2565f46a221bSXiaojian Du void vangogh_set_ppt_funcs(struct smu_context *smu)
2566f46a221bSXiaojian Du {
2567f46a221bSXiaojian Du smu->ppt_funcs = &vangogh_ppt_funcs;
2568f46a221bSXiaojian Du smu->message_map = vangogh_message_map;
2569f46a221bSXiaojian Du smu->feature_map = vangogh_feature_mask_map;
2570f46a221bSXiaojian Du smu->table_map = vangogh_table_map;
2571ec3b35c8SXiaojian Du smu->workload_map = vangogh_workload_map;
2572f46a221bSXiaojian Du smu->is_apu = true;
2573da1db031SAlex Deucher smu_v11_0_set_smu_mailbox_registers(smu);
2574f46a221bSXiaojian Du }
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