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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c37 for (i = 0; i < 64; i++) { in gk104_top_parse()
41 type = ~0; in gk104_top_parse()
42 inst = 0; in gk104_top_parse()
45 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_parse()
47 switch (data & 0x00000003) { in gk104_top_parse()
48 case 0x00000000: /* NOT_VALID */ in gk104_top_parse()
50 case 0x00000001: /* DATA */ in gk104_top_parse()
51 inst = (data & 0x3c000000) >> 26; in gk104_top_parse()
52 info->addr = (data & 0x00fff000); in gk104_top_parse()
53 if (data & 0x00000004) in gk104_top_parse()
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dk3-ringacc.yaml84 reg = <0x0 0x3c000000 0x0 0x400000>,
85 <0x0 0x38000000 0x0 0x400000>,
86 <0x0 0x31120000 0x0 0x100>,
87 <0x0 0x33000000 0x0 0x40000>,
88 <0x0 0x31080000 0x0 0x40000>;
91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8812a.c21 s8 rx_pwr_all = 0; in rtw8812a_cck_rx_pwr()
48 case 0: in rtw8812a_cck_rx_pwr()
85 cont_tx = rtw_read32_mask(rtwdev, REG_SINGLE_TONE_CONT_TX, 0x70000); in rtw8812a_do_lck()
90 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); in rtw8812a_do_lck()
94 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000, 1); in rtw8812a_do_lck()
98 for (i = 0; i < 5; i++) { in rtw8812a_do_lck()
99 if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000) != 1) in rtw8812a_do_lck()
110 rtw_write_rf(rtwdev, RF_PATH_A, RF_LCK, BIT(14), 0); in rtw8812a_do_lck()
113 rtw_write8(rtwdev, REG_TXPAUSE, 0); in rtw8812a_do_lck()
124 /* [31] = 0 --> Page C */ in rtw8812a_iqk_backup_rf()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-mek.dts27 mboxes = <&lsio_mu5 0 1
34 fsl,entry-address = <0x34fe0000>;
40 reg = <0x00000000 0x80000000 0 0x40000000>;
55 pinctrl-0 = <&pinctrl_typec_mux>;
69 mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */
72 #size-cells = <0>;
74 i2c@0 {
75 reg = <0>;
77 #size-cells = <0>;
81 reg = <0x1a>;
[all …]
H A Dimx8qm-mek.dts32 reg = <0x00000000 0x80000000 0 0x40000000>;
37 #clock-cells = <0>;
48 reg = <0 0x90000000 0 0x8000>;
53 reg = <0 0x90008000 0 0x8000>;
58 reg = <0 0x90010000 0 0x8000>;
63 reg = <0 0x90018000 0 0x8000>;
68 reg = <0 0x900ff000 0 0x1000>;
73 reg = <0 0x90100000 0 0x8000>;
78 reg = <0 0x90108000 0 0x8000>;
83 reg = <0 0x90110000 0 0x8000>;
[all …]
H A Dimx95-phycore-fpsc.dtsi26 reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
41 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
57 alloc-ranges = <0 0x80000000 0 0x7f000000>;
59 size = <0 0x3c000000>;
67 pinctrl-0 = <&pinctrl_enetc0>;
74 pinctrl-0 = <&pinctrl_enetc1>;
80 pinctrl-0 = <&pinctrl_flexcan1>;
85 pinctrl-0 = <&pinctrl_flexcan2>;
90 pinctrl-0 = <&pinctrl_flexspi>;
98 pinctrl-0 = <&pinctrl_gpio1>;
[all …]
H A Dimx95-19x19-verdin-evk.dts15 #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
16 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
17 #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
18 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
19 #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
53 reg = <0x0 0x80000000 0 0x80000000>;
63 alloc-ranges = <0 0x80000000 0 0x7f000000>;
64 size = <0 0x3c000000>;
105 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
134 pinctrl-0 = <&pinctrl_enetc0>;
[all …]
H A Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
21 pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
76 pinctrl-0 = <&pinctrl_wifi_pdn>;
87 pinctrl-0 = <&pinctrl_gpio7>;
99 pinctrl-0 = <&pinctrl_usbh_en>;
136 reg = <0 0x84000000 0 0x2000000>;
141 reg = <0 0x86000000 0 0x200000>;
[all …]
H A Dimx95-19x19-evk.dts15 #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
16 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
17 #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
18 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
19 #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
57 reg = <0x0 0x80000000 0 0x80000000>;
74 alloc-ranges = <0 0x80000000 0 0x7f000000>;
75 size = <0 0x3c000000>;
83 #phy-cells = <0>;
91 #phy-cells = <0>;
[all …]
H A Dimx95-15x15-evk.dts15 #define FALLING_EDGE BIT(0)
18 #define BRD_SM_CTRL_SD3_WAKE 0x8000
19 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001
20 #define BRD_SM_CTRL_BT_WAKE 0x8002
21 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003
22 #define BRD_SM_CTRL_BUTTON 0x8004
67 pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>;
107 gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>;
131 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
152 * the SDIO3.0 switch voltage.
[all …]
H A Dimx95-toradex-smarc.dtsi34 #clock-cells = <0>;
40 #clock-cells = <0>;
114 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
127 pinctrl-0 = <&pinctrl_usdhc2_vsel>;
131 states = <1800000 0x1>,
132 <3300000 0x0>;
155 size = <0 0x3c000000>;
156 alloc-ranges = <0 0x80000000 0 0x7F000000>;
165 pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>;
173 pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>;
[all …]
/linux/drivers/regulator/
H A Dqcom_rpm-regulator.c67 .mV = { 0, 0x00000FFF, 0 },
68 .ip = { 0, 0x00FFF000, 12 },
69 .fm = { 0, 0x03000000, 24 },
70 .pc = { 0, 0x3C000000, 26 },
71 .pf = { 0, 0xC0000000, 30 },
72 .pd = { 1, 0x00000001, 0 },
73 .ia = { 1, 0x00001FFE, 1 },
78 .mV = { 0, 0x00000FFF, 0 },
79 .ip = { 0, 0x00FFF000, 12 },
80 .fm = { 0, 0x03000000, 24 },
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
52 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 {
69 reg = <0 0 0 0 0>;
75 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x38000000 0x800000>;
113 reg = <0x3c000000 0x4000000>;
121 reg = <0x3a000000 0x10000>;
[all …]
/linux/drivers/message/fusion/lsi/
H A Dmpi_init.h88 U8 LUN[8]; /* 0Ch */
100 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
101 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
102 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
104 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
105 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
106 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
108 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
112 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
113 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]

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