1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 NXP 4 * Copyright 2025 Marek Vasut <marek.vasut@mailbox.org> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx95.dtsi" 11 12#define FALLING_EDGE 1 13#define RISING_EDGE 2 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 16#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 18#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 20 21/ { 22 model = "i.MX 95 Verdin Evaluation Kit (EVK)"; 23 compatible = "toradex,verdin-imx95-19x19-evk", "fsl,imx95"; 24 25 aliases { 26 ethernet0 = &enetc_port0; 27 ethernet1 = &enetc_port1; 28 ethernet2 = &enetc_port2; 29 gpio0 = &gpio1; 30 gpio1 = &gpio2; 31 gpio2 = &gpio3; 32 gpio3 = &gpio4; 33 gpio4 = &gpio5; 34 i2c0 = &lpi2c1; 35 i2c1 = &lpi2c2; 36 i2c2 = &lpi2c3; 37 i2c3 = &lpi2c4; 38 i2c4 = &lpi2c5; 39 i2c5 = &lpi2c6; 40 i2c6 = &lpi2c7; 41 i2c7 = &lpi2c8; 42 mmc0 = &usdhc1; 43 mmc1 = &usdhc2; 44 serial0 = &lpuart1; 45 }; 46 47 chosen { 48 stdout-path = &lpuart1; 49 }; 50 51 memory@80000000 { 52 device_type = "memory"; 53 reg = <0x0 0x80000000 0 0x80000000>; 54 }; 55 56 reserved-memory { 57 #address-cells = <2>; 58 #size-cells = <2>; 59 ranges; 60 61 linux_cma: linux,cma { 62 compatible = "shared-dma-pool"; 63 alloc-ranges = <0 0x80000000 0 0x7f000000>; 64 size = <0 0x3c000000>; 65 linux,cma-default; 66 reusable; 67 }; 68 }; 69 70 reg_1p8v: regulator-1p8v { 71 compatible = "regulator-fixed"; 72 regulator-max-microvolt = <1800000>; 73 regulator-min-microvolt = <1800000>; 74 regulator-name = "+V1.8_SW"; 75 }; 76 77 reg_3p3v: regulator-3p3v { 78 compatible = "regulator-fixed"; 79 regulator-max-microvolt = <3300000>; 80 regulator-min-microvolt = <3300000>; 81 regulator-name = "+V3.3_SW"; 82 }; 83 84 reg_m2_pwr: regulator-m2-pwr { 85 compatible = "regulator-fixed"; 86 regulator-name = "M.2-power"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 gpio = <&gpio2 4 GPIO_ACTIVE_LOW>; 90 }; 91 92 reg_pcie0: regulator-pcie { 93 compatible = "regulator-fixed"; 94 regulator-name = "PCIE_WLAN_EN"; 95 regulator-min-microvolt = <3300000>; 96 regulator-max-microvolt = <3300000>; 97 vin-supply = <®_m2_pwr>; 98 gpio = <&i2c7_pcal6524 18 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 }; 101 102 reg_usdhc2_vmmc: regulator-usdhc2 { 103 compatible = "regulator-fixed"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 106 regulator-name = "VDD_SD2_3V3"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 110 enable-active-high; 111 off-on-delay-us = <12000>; 112 }; 113 114 usdhc3_pwrseq: usdhc3-pwrseq { 115 compatible = "mmc-pwrseq-simple"; 116 reset-gpios = <&i2c7_pcal6524 11 GPIO_ACTIVE_HIGH>; 117 }; 118 119 sound-wm8904 { 120 compatible = "fsl,imx-audio-wm8904"; 121 model = "wm8904-audio"; 122 audio-cpu = <&sai3>; 123 audio-codec = <&wm8904>; 124 audio-routing = 125 "Headphone Jack", "HPOUTL", 126 "Headphone Jack", "HPOUTR", 127 "AMIC", "MICBIAS", 128 "IN2L", "AMIC"; 129 }; 130}; 131 132&enetc_port0 { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_enetc0>; 135 phy-handle = <ðphy0>; 136 phy-mode = "rgmii-id"; 137 status = "okay"; 138}; 139 140&flexspi1 { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_flexspi1>; 143 status = "okay"; 144 145 flash@0 { 146 compatible = "jedec,spi-nor"; 147 reg = <0>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_flexspi1_reset>; 150 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 spi-max-frequency = <200000000>; 154 spi-tx-bus-width = <8>; 155 spi-rx-bus-width = <8>; 156 }; 157}; 158 159&lpi2c4 { 160 clock-frequency = <400000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_lpi2c4>; 163 status = "okay"; 164 165 wm8904: codec@1a { 166 #sound-dai-cells = <0>; 167 compatible = "wlf,wm8904"; 168 reg = <0x1a>; 169 clocks = <&scmi_clk IMX95_CLK_SAI3>; 170 clock-names = "mclk"; 171 AVDD-supply = <®_1p8v>; 172 CPVDD-supply = <®_1p8v>; 173 DBVDD-supply = <®_1p8v>; 174 DCVDD-supply = <®_1p8v>; 175 MICVDD-supply = <®_1p8v>; 176 }; 177}; 178 179&lpi2c5 { 180 clock-frequency = <100000>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_lpi2c5>; 183 status = "okay"; 184}; 185 186&lpi2c6 { 187 clock-frequency = <100000>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_lpi2c6>; 190 status = "okay"; 191}; 192 193&lpi2c7 { 194 clock-frequency = <1000000>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_lpi2c7>; 197 status = "okay"; 198 199 i2c7_pcal6524: i2c7-gpio@23 { 200 compatible = "nxp,pcal6524"; 201 reg = <0x23>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 interrupt-parent = <&gpio5>; 209 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 210 }; 211 212 /* Current measurement at SoM 5V power output */ 213 hwmon@41 { 214 compatible = "ti,ina219"; 215 reg = <0x41>; 216 shunt-resistor = <10000>; 217 }; 218 219 /* Current measurement at Board power input */ 220 hwmon@45 { 221 compatible = "ti,ina219"; 222 reg = <0x45>; 223 shunt-resistor = <10000>; 224 }; 225 226 eeprom@50 { 227 compatible = "st,24c02"; 228 reg = <0x50>; 229 }; 230 231 ptn5110: tcpc@52 { 232 compatible = "nxp,ptn5110", "tcpci"; 233 reg = <0x52>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_typec>; 236 interrupt-parent = <&gpio5>; 237 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 238 239 typec_con: connector { 240 compatible = "usb-c-connector"; 241 label = "USB-C"; 242 power-role = "dual"; 243 data-role = "dual"; 244 try-power-role = "sink"; 245 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 246 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 247 PDO_VAR(5000, 20000, 3000)>; 248 op-sink-microwatt = <15000000>; 249 self-powered; 250 251 ports { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 port@0 { 256 reg = <0>; 257 258 typec_con_hs: endpoint { 259 remote-endpoint = <&usb3_data_hs>; 260 }; 261 }; 262 263 port@1 { 264 reg = <1>; 265 266 typec_con_ss: endpoint { 267 remote-endpoint = <&usb3_data_ss>; 268 }; 269 }; 270 }; 271 }; 272 }; 273}; 274 275&lpuart1 { 276 /* console */ 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_uart1>; 279 status = "okay"; 280}; 281 282&mu7 { 283 status = "okay"; 284}; 285 286&netcmix_blk_ctrl { 287 status = "okay"; 288}; 289 290&netc_blk_ctrl { 291 status = "okay"; 292}; 293 294&netc_emdio { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_emdio>; 297 status = "okay"; 298 299 ethphy0: ethernet-phy@1 { 300 reg = <1>; 301 realtek,clkout-disable; 302 }; 303}; 304 305&pcie0 { 306 pinctrl-0 = <&pinctrl_pcie0>; 307 pinctrl-names = "default"; 308 reset-gpio = <&i2c7_pcal6524 17 GPIO_ACTIVE_LOW>; 309 vpcie-supply = <®_pcie0>; 310 status = "okay"; 311}; 312 313&pcie1 { 314 pinctrl-0 = <&pinctrl_pcie1>; 315 pinctrl-names = "default"; 316 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 317 status = "okay"; 318}; 319 320&sai1 { 321 #sound-dai-cells = <0>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_sai1>; 324 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 325 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 326 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 327 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 328 <&scmi_clk IMX95_CLK_SAI1>; 329 assigned-clock-parents = <0>, <0>, <0>, <0>, 330 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 331 assigned-clock-rates = <3932160000>, 332 <3612672000>, <393216000>, 333 <361267200>, <12288000>; 334 fsl,sai-mclk-direction-output; 335 status = "okay"; 336}; 337 338&sai3 { 339 #sound-dai-cells = <0>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_sai3>; 342 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 343 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 344 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 345 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 346 <&scmi_clk IMX95_CLK_SAI3>; 347 assigned-clock-parents = <0>, <0>, <0>, <0>, 348 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 349 assigned-clock-rates = <3932160000>, 350 <3612672000>, <393216000>, 351 <361267200>, <12288000>; 352 fsl,sai-mclk-direction-output; 353 status = "okay"; 354}; 355 356&usb3 { 357 status = "okay"; 358}; 359 360&usb3_dwc3 { 361 dr_mode = "otg"; 362 hnp-disable; 363 srp-disable; 364 adp-disable; 365 usb-role-switch; 366 role-switch-default-mode = "peripheral"; 367 snps,dis-u1-entry-quirk; 368 snps,dis-u2-entry-quirk; 369 status = "okay"; 370 371 port { 372 usb3_data_hs: endpoint { 373 remote-endpoint = <&typec_con_hs>; 374 }; 375 }; 376}; 377 378&usb3_phy { 379 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 380 orientation-switch; 381 status = "okay"; 382 383 port { 384 usb3_data_ss: endpoint { 385 remote-endpoint = <&typec_con_ss>; 386 }; 387 }; 388}; 389 390&usdhc1 { 391 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 392 pinctrl-0 = <&pinctrl_usdhc1>; 393 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 394 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 395 pinctrl-3 = <&pinctrl_usdhc1>; 396 bus-width = <8>; 397 non-removable; 398 no-sdio; 399 no-sd; 400 status = "okay"; 401}; 402 403&usdhc2 { 404 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 405 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 406 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 407 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 408 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 409 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 410 vmmc-supply = <®_usdhc2_vmmc>; 411 bus-width = <4>; 412 status = "okay"; 413}; 414 415&usdhc3 { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_usdhc3>; 418 mmc-pwrseq = <&usdhc3_pwrseq>; 419 vmmc-supply = <®_pcie0>; 420 bus-width = <4>; 421 keep-power-in-suspend; 422 non-removable; 423 status = "okay"; 424}; 425 426&scmi_misc { 427 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 428 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 429 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 430 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 431 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 432}; 433 434&wdog3 { 435 fsl,ext-reset-output; 436 status = "okay"; 437}; 438 439&scmi_iomuxc { 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_hog>; 442 443 pinctrl_hog: hoggrp { 444 fsl,pins = 445 <IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe>; 446 }; 447 448 pinctrl_emdio: emdiogrp { 449 fsl,pins = 450 <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, 451 <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; 452 }; 453 454 pinctrl_enetc0: enetc0grp { 455 fsl,pins = 456 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e>, 457 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e>, 458 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e>, 459 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e>, 460 <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, 461 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, 462 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, 463 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, 464 <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, 465 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, 466 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, 467 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; 468 }; 469 470 pinctrl_flexspi1: flexspi1grp { 471 fsl,pins = 472 <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, 473 <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, 474 <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>, 475 <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, 476 <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, 477 <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, 478 <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, 479 <IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, 480 <IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, 481 <IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, 482 <IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>; 483 }; 484 485 pinctrl_flexspi1_reset: flexspi1-reset-grp { 486 fsl,pins = 487 <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; 488 }; 489 490 pinctrl_hp: hpgrp { 491 fsl,pins = 492 <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; 493 }; 494 495 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 496 fsl,pins = 497 <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e>; 498 }; 499 500 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 501 fsl,pins = 502 <IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e>; 503 }; 504 505 pinctrl_lpi2c4: lpi2c4grp { 506 fsl,pins = 507 <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e>, 508 <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e>; 509 }; 510 511 pinctrl_lpi2c5: lpi2c5grp { 512 fsl,pins = 513 <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e>, 514 <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e>; 515 }; 516 517 pinctrl_lpi2c6: lpi2c6grp { 518 fsl,pins = 519 <IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e>, 520 <IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e>; 521 }; 522 523 pinctrl_lpi2c7: lpi2c7grp { 524 fsl,pins = 525 <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e>, 526 <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e>; 527 }; 528 529 pinctrl_pcal6416: pcal6416grp { 530 fsl,pins = 531 <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; 532 }; 533 534 pinctrl_pcie0: pcie0grp { 535 fsl,pins = 536 <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e>; 537 }; 538 539 pinctrl_pcie1: pcie1grp { 540 fsl,pins = 541 <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e>; 542 }; 543 544 pinctrl_pdm: pdmgrp { 545 fsl,pins = 546 <IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e>, 547 <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e>; 548 }; 549 550 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 551 fsl,pins = 552 <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e>; 553 }; 554 555 pinctrl_sai1: sai1grp { 556 fsl,pins = 557 <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e>, 558 <IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e>, 559 <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e>, 560 <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e>; 561 }; 562 563 pinctrl_sai2: sai2grp { 564 fsl,pins = 565 <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e>, 566 <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e>, 567 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e>, 568 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e>, 569 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e>, 570 <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e>, 571 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e>, 572 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e>, 573 <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e>, 574 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e>, 575 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; 576 }; 577 578 pinctrl_sai3: sai3grp { 579 fsl,pins = 580 <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>, 581 <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e>, 582 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e>, 583 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e>, 584 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e>; 585 }; 586 587 pinctrl_tpm6: tpm6grp { 588 fsl,pins = 589 <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e>; 590 }; 591 592 pinctrl_typec: typecgrp { 593 fsl,pins = 594 <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; 595 }; 596 597 pinctrl_uart1: uart1grp { 598 fsl,pins = 599 <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, 600 <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; 601 }; 602 603 pinctrl_usdhc1: usdhc1grp { 604 fsl,pins = 605 <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, 606 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, 607 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, 608 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, 609 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, 610 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, 611 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, 612 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, 613 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, 614 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, 615 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; 616 }; 617 618 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 619 fsl,pins = 620 <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, 621 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, 622 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, 623 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, 624 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, 625 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, 626 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, 627 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, 628 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, 629 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, 630 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; 631 }; 632 633 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 634 fsl,pins = 635 <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, 636 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, 637 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, 638 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, 639 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, 640 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, 641 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, 642 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, 643 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, 644 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, 645 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; 646 }; 647 648 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 649 fsl,pins = 650 <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e>; 651 }; 652 653 pinctrl_usdhc2: usdhc2grp { 654 fsl,pins = 655 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, 656 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, 657 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, 658 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, 659 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, 660 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>, 661 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 662 }; 663 664 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 665 fsl,pins = 666 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, 667 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, 668 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, 669 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, 670 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, 671 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>, 672 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 673 }; 674 675 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 676 fsl,pins = 677 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, 678 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, 679 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, 680 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, 681 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, 682 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>, 683 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 684 }; 685 686 pinctrl_usdhc3: usdhc3grp { 687 fsl,pins = 688 <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, 689 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, 690 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, 691 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, 692 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, 693 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; 694 }; 695}; 696