1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/i3c/i3c.h> 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/phy/phy-imx8-pcie.h> 11#include <dt-bindings/pwm/pwm.h> 12#include <dt-bindings/usb/pd.h> 13#include "imx95.dtsi" 14 15#define FALLING_EDGE BIT(0) 16#define RISING_EDGE BIT(1) 17 18#define BRD_SM_CTRL_SD3_WAKE 0x8000 19#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 20#define BRD_SM_CTRL_BT_WAKE 0x8002 21#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 22#define BRD_SM_CTRL_BUTTON 0x8004 23 24/ { 25 compatible = "fsl,imx95-15x15-evk", "fsl,imx95"; 26 model = "NXP i.MX95 15X15 board"; 27 28 aliases { 29 ethernet0 = &enetc_port0; 30 ethernet1 = &enetc_port1; 31 serial0 = &lpuart1; 32 }; 33 34 bt_sco_codec: bt-sco-codec { 35 compatible = "linux,bt-sco"; 36 #sound-dai-cells = <1>; 37 }; 38 39 chosen { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 stdout-path = &lpuart1; 43 }; 44 45 fan0: pwm-fan { 46 compatible = "pwm-fan"; 47 #cooling-cells = <2>; 48 cooling-levels = <64 128 192 255>; 49 pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; 50 }; 51 52 reg_1p8v: regulator-1p8v { 53 compatible = "regulator-fixed"; 54 regulator-max-microvolt = <1800000>; 55 regulator-min-microvolt = <1800000>; 56 regulator-name = "+V1.8_SW"; 57 }; 58 59 reg_3p3v: regulator-3p3v { 60 compatible = "regulator-fixed"; 61 regulator-max-microvolt = <3300000>; 62 regulator-min-microvolt = <3300000>; 63 regulator-name = "+V3.3_SW"; 64 }; 65 66 reg_vref_1v8: regulator-adc-vref { 67 compatible = "regulator-fixed"; 68 regulator-max-microvolt = <1800000>; 69 regulator-min-microvolt = <1800000>; 70 regulator-name = "vref_1v8"; 71 }; 72 73 reg_audio_pwr: regulator-audio-pwr { 74 compatible = "regulator-fixed"; 75 regulator-always-on; 76 regulator-max-microvolt = <3300000>; 77 regulator-min-microvolt = <3300000>; 78 regulator-name = "audio-pwr"; 79 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_audio_switch1: regulator-audio-switch1 { 84 compatible = "regulator-fixed"; 85 regulator-always-on; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "audio-switch1"; 89 gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; 90 }; 91 92 reg_can2_stby: regulator-can2-stby { 93 compatible = "regulator-fixed"; 94 regulator-max-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>; 96 regulator-name = "can2-stby"; 97 gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; 98 }; 99 100 reg_m2_pwr: regulator-m2-pwr { 101 compatible = "regulator-fixed"; 102 regulator-always-on; 103 regulator-max-microvolt = <3300000>; 104 regulator-min-microvolt = <3300000>; 105 regulator-name = "M.2-power"; 106 gpio = <&pcal6524 10 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_usdhc2_vmmc: regulator-usdhc2 { 111 compatible = "regulator-fixed"; 112 off-on-delay-us = <12000>; 113 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 114 pinctrl-names = "default"; 115 regulator-max-microvolt = <3300000>; 116 regulator-min-microvolt = <3300000>; 117 regulator-name = "VDD_SD2_3V3"; 118 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 119 enable-active-high; 120 }; 121 122 reg_usdhc3_vmmc: regulator-usdhc3 { 123 compatible = "regulator-fixed"; 124 regulator-max-microvolt = <3300000>; 125 regulator-min-microvolt = <3300000>; 126 regulator-name = "WLAN_EN"; 127 vin-supply = <®_m2_pwr>; 128 gpio = <&pcal6524 11 GPIO_ACTIVE_HIGH>; 129 enable-active-high; 130 /* 131 * IW612 wifi chip needs more delay than other wifi chips to complete 132 * the host interface initialization after power up, otherwise the 133 * internal state of IW612 may be unstable, resulting in the failure of 134 * the SDIO3.0 switch voltage. 135 */ 136 startup-delay-us = <20000>; 137 }; 138 139 reg_usb_vbus: regulator-vbus { 140 compatible = "regulator-fixed"; 141 regulator-name = "USB_VBUS"; 142 regulator-min-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>; 144 gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; 145 enable-active-high; 146 }; 147 148 reg_vcc_12v: regulator-vcc-12v { 149 compatible = "regulator-fixed"; 150 regulator-max-microvolt = <12000000>; 151 regulator-min-microvolt = <12000000>; 152 regulator-name = "VCC_12V"; 153 gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; 154 enable-active-high; 155 }; 156 157 reserved-memory { 158 ranges; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 162 linux_cma: linux,cma { 163 compatible = "shared-dma-pool"; 164 alloc-ranges = <0 0x80000000 0 0x7F000000>; 165 reusable; 166 size = <0 0x3c000000>; 167 linux,cma-default; 168 }; 169 170 vdev0vring0: vdev0vring0@88000000 { 171 reg = <0 0x88000000 0 0x8000>; 172 no-map; 173 }; 174 175 vdev0vring1: vdev0vring1@88008000 { 176 reg = <0 0x88008000 0 0x8000>; 177 no-map; 178 }; 179 180 vdev1vring0: vdev1vring0@88010000 { 181 reg = <0 0x88010000 0 0x8000>; 182 no-map; 183 }; 184 185 vdev1vring1: vdev1vring1@88018000 { 186 reg = <0 0x88018000 0 0x8000>; 187 no-map; 188 }; 189 190 vdevbuffer: vdevbuffer@88020000 { 191 compatible = "shared-dma-pool"; 192 reg = <0 0x88020000 0 0x100000>; 193 no-map; 194 }; 195 196 rsc_table: rsc-table@88220000 { 197 reg = <0 0x88220000 0 0x1000>; 198 no-map; 199 }; 200 201 vpu_boot: vpu_boot@a0000000 { 202 reg = <0 0xa0000000 0 0x100000>; 203 no-map; 204 }; 205 }; 206 207 sound-bt-sco { 208 compatible = "simple-audio-card"; 209 simple-audio-card,bitclock-inversion; 210 simple-audio-card,bitclock-master = <&btcpu>; 211 simple-audio-card,format = "dsp_a"; 212 simple-audio-card,frame-master = <&btcpu>; 213 simple-audio-card,name = "bt-sco-audio"; 214 215 simple-audio-card,codec { 216 sound-dai = <&bt_sco_codec 1>; 217 }; 218 219 btcpu: simple-audio-card,cpu { 220 dai-tdm-slot-num = <2>; 221 dai-tdm-slot-width = <16>; 222 sound-dai = <&sai1>; 223 }; 224 }; 225 226 sound-micfil { 227 compatible = "fsl,imx-audio-card"; 228 model = "micfil-audio"; 229 230 pri-dai-link { 231 format = "i2s"; 232 link-name = "micfil hifi"; 233 234 cpu { 235 sound-dai = <&micfil>; 236 }; 237 }; 238 }; 239 240 sound-wm8962 { 241 compatible = "fsl,imx-audio-wm8962"; 242 audio-codec = <&wm8962>; 243 audio-cpu = <&sai3>; 244 audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", 245 "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", 246 "IN3R", "AMIC", "IN1R", "AMIC"; 247 hp-det-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; 248 model = "wm8962-audio"; 249 pinctrl-0 = <&pinctrl_hp>; 250 pinctrl-names = "default"; 251 }; 252 253 sound-xcvr { 254 compatible = "fsl,imx-audio-card"; 255 model = "imx-audio-xcvr"; 256 257 pri-dai-link { 258 link-name = "XCVR PCM"; 259 260 cpu { 261 sound-dai = <&xcvr>; 262 }; 263 }; 264 }; 265 266 usdhc3_pwrseq: usdhc3-pwrseq { 267 compatible = "mmc-pwrseq-simple"; 268 pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; 269 pinctrl-names = "default"; 270 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 271 }; 272 273 memory@80000000 { 274 reg = <0x0 0x80000000 0 0x80000000>; 275 device_type = "memory"; 276 }; 277}; 278 279&adc1 { 280 vref-supply = <®_vref_1v8>; 281 status = "okay"; 282}; 283 284&enetc_port0 { 285 phy-handle = <ðphy0>; 286 phy-mode = "rgmii-id"; 287 pinctrl-0 = <&pinctrl_enetc0>; 288 pinctrl-names = "default"; 289 status = "okay"; 290}; 291 292&enetc_port1 { 293 phy-handle = <ðphy1>; 294 phy-mode = "rgmii-id"; 295 pinctrl-0 = <&pinctrl_enetc1>; 296 pinctrl-names = "default"; 297 status = "okay"; 298}; 299 300&flexcan2 { 301 pinctrl-0 = <&pinctrl_flexcan2>; 302 pinctrl-names = "default"; 303 xceiver-supply = <®_can2_stby>; 304 status = "okay"; 305}; 306 307&i3c2 { 308 i2c-scl-hz = <400000>; 309 pinctrl-0 = <&pinctrl_i3c2>; 310 pinctrl-names = "default"; 311 status = "okay"; 312 313 pca9570: gpio@24 { 314 compatible = "nxp,pca9570"; 315 reg = <0x24 0 (I2C_FILTER)>; 316 #gpio-cells = <2>; 317 gpio-controller; 318 gpio-line-names = "OUT1", "OUT2", "OUT3", "OUT4"; 319 }; 320}; 321 322&lpi2c2 { 323 clock-frequency = <400000>; 324 pinctrl-0 = <&pinctrl_lpi2c2>; 325 pinctrl-names = "default"; 326 status = "okay"; 327 328 wm8962: codec@1a { 329 compatible = "wlf,wm8962"; 330 reg = <0x1a>; 331 clocks = <&scmi_clk IMX95_CLK_SAI3>; 332 AVDD-supply = <®_audio_pwr>; 333 CPVDD-supply = <®_audio_pwr>; 334 DBVDD-supply = <®_audio_pwr>; 335 DCVDD-supply = <®_audio_pwr>; 336 gpio-cfg = < 337 0x0000 338 0x0000 339 0x0000 340 0x0000 341 0x0000 342 0x0000 343 >; 344 MICVDD-supply = <®_audio_pwr>; 345 PLLVDD-supply = <®_audio_pwr>; 346 SPKVDD1-supply = <®_audio_pwr>; 347 SPKVDD2-supply = <®_audio_pwr>; 348 }; 349 350 pcal6524: gpio@22 { 351 compatible = "nxp,pcal6524"; 352 reg = <0x22>; 353 #interrupt-cells = <2>; 354 interrupt-controller; 355 interrupt-parent = <&gpio5>; 356 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 357 #gpio-cells = <2>; 358 gpio-controller; 359 pinctrl-0 = <&pinctrl_pcal6524>; 360 pinctrl-names = "default"; 361 }; 362}; 363 364&lpi2c3 { 365 clock-frequency = <400000>; 366 pinctrl-0 = <&pinctrl_lpi2c3>; 367 pinctrl-names = "default"; 368 status = "okay"; 369 370 ptn5110: tcpc@50 { 371 compatible = "nxp,ptn5110", "tcpci"; 372 reg = <0x50>; 373 interrupt-parent = <&gpio5>; 374 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 375 pinctrl-0 = <&pinctrl_ptn5110>; 376 pinctrl-names = "default"; 377 378 typec_con: connector { 379 compatible = "usb-c-connector"; 380 data-role = "dual"; 381 label = "USB-C"; 382 op-sink-microwatt = <15000000>; 383 power-role = "dual"; 384 self-powered; 385 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 386 PDO_VAR(5000, 20000, 3000)>; 387 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 388 try-power-role = "sink"; 389 390 ports { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 port@0 { 395 reg = <0>; 396 397 typec_con_hs: endpoint { 398 remote-endpoint = <&usb3_data_hs>; 399 }; 400 }; 401 402 port@1 { 403 reg = <1>; 404 405 typec_con_ss: endpoint { 406 remote-endpoint = <&usb3_data_ss>; 407 }; 408 }; 409 }; 410 }; 411 }; 412 413 pca9632: led-controller@62 { 414 compatible = "nxp,pca9632"; 415 reg = <0x62>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 nxp,inverted-out; 419 420 led_backlight0: led@0 { 421 reg = <0>; 422 color = <LED_COLOR_ID_WHITE>; 423 function = LED_FUNCTION_BACKLIGHT; 424 function-enumerator = <0>; 425 }; 426 427 led_backlight1: led@1 { 428 reg = <1>; 429 color = <LED_COLOR_ID_WHITE>; 430 function = LED_FUNCTION_BACKLIGHT; 431 function-enumerator = <1>; 432 }; 433 }; 434}; 435 436&lpi2c4 { 437 clock-frequency = <400000>; 438 pinctrl-0 = <&pinctrl_lpi2c4>; 439 pinctrl-names = "default"; 440 status = "okay"; 441}; 442 443&lpi2c6 { 444 clock-frequency = <100000>; 445 pinctrl-0 = <&pinctrl_lpi2c6>; 446 pinctrl-names = "default"; 447 status = "okay"; 448}; 449 450&lpuart1 { 451 pinctrl-0 = <&pinctrl_uart1>; 452 pinctrl-names = "default"; 453 status = "okay"; 454}; 455 456&lpuart5 { 457 pinctrl-0 = <&pinctrl_uart5>; 458 pinctrl-names = "default"; 459 status = "okay"; 460 461 bluetooth { 462 compatible = "nxp,88w8987-bt"; 463 }; 464}; 465 466&micfil { 467 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 468 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 469 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 470 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 471 <&scmi_clk IMX95_CLK_PDM>; 472 assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; 473 assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <49152000>; 474 #sound-dai-cells = <0>; 475 pinctrl-0 = <&pinctrl_pdm>; 476 pinctrl-names = "default"; 477 status = "okay"; 478}; 479 480&mu7 { 481 status = "okay"; 482}; 483 484&netc_blk_ctrl { 485 status = "okay"; 486}; 487 488&netc_bus0 { 489 msi-map = <0x00 &its 0x60 0x1>, //ENETC0 PF 490 <0x10 &its 0x61 0x1>, //ENETC0 VF0 491 <0x20 &its 0x62 0x1>, //ENETC0 VF1 492 <0x40 &its 0x63 0x1>, //ENETC1 PF 493 <0x50 &its 0x65 0x1>, //ENETC1 VF0 494 <0x60 &its 0x66 0x1>, //ENETC1 VF1 495 <0x80 &its 0x64 0x1>, //ENETC2 PF 496 <0xc0 &its 0x67 0x1>; 497 iommu-map = <0x0 &smmu 0x20 0x1>, 498 <0x10 &smmu 0x21 0x1>, 499 <0x20 &smmu 0x22 0x1>, 500 <0x40 &smmu 0x23 0x1>, 501 <0x50 &smmu 0x25 0x1>, 502 <0x60 &smmu 0x26 0x1>, 503 <0x80 &smmu 0x24 0x1>, 504 <0xc0 &smmu 0x27 0x1>; 505}; 506 507&netc_emdio { 508 pinctrl-0 = <&pinctrl_emdio>; 509 pinctrl-names = "default"; 510 status = "okay"; 511 512 ethphy0: ethernet-phy@1 { 513 reg = <1>; 514 reset-assert-us = <10000>; 515 reset-deassert-us = <80000>; 516 reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; 517 realtek,clkout-disable; 518 }; 519 520 ethphy1: ethernet-phy@2 { 521 reg = <2>; 522 reset-assert-us = <10000>; 523 reset-deassert-us = <80000>; 524 reset-gpios = <&pcal6524 5 GPIO_ACTIVE_LOW>; 525 realtek,clkout-disable; 526 }; 527}; 528 529&netc_timer { 530 status = "okay"; 531}; 532 533&netcmix_blk_ctrl { 534 status = "okay"; 535}; 536 537&pcie0 { 538 pinctrl-0 = <&pinctrl_pcie0>; 539 pinctrl-names = "default"; 540 reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; 541 vpcie-supply = <®_m2_pwr>; 542 status = "okay"; 543}; 544 545&pcie0_ep { 546 pinctrl-0 = <&pinctrl_pcie0>; 547 pinctrl-names = "default"; 548 vpcie-supply = <®_m2_pwr>; 549 status = "disabled"; 550}; 551 552&sai1 { 553 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 554 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 555 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 556 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 557 <&scmi_clk IMX95_CLK_SAI1>; 558 assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; 559 assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; 560 #sound-dai-cells = <0>; 561 pinctrl-0 = <&pinctrl_sai1>; 562 pinctrl-names = "default"; 563 fsl,sai-mclk-direction-output; 564 status = "okay"; 565}; 566 567&sai3 { 568 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 569 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 570 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 571 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 572 <&scmi_clk IMX95_CLK_SAI3>; 573 assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; 574 assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; 575 #sound-dai-cells = <0>; 576 pinctrl-0 = <&pinctrl_sai3>; 577 pinctrl-names = "default"; 578 fsl,sai-mclk-direction-output; 579 status = "okay"; 580}; 581 582&scmi_iomuxc { 583 pinctrl_emdio: emdiogrp { 584 fsl,pins = < 585 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e 586 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 587 >; 588 }; 589 590 pinctrl_enetc0: enetc0grp { 591 fsl,pins = < 592 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 593 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 594 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 595 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 596 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 597 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 598 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 599 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 600 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 601 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 602 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 603 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 604 >; 605 }; 606 607 pinctrl_enetc1: enetc1grp { 608 fsl,pins = < 609 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e 610 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e 611 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e 612 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e 613 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 614 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e 615 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e 616 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e 617 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e 618 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e 619 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e 620 IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e 621 >; 622 }; 623 624 pinctrl_flexcan2: flexcan2grp { 625 fsl,pins = < 626 IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e 627 IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e 628 >; 629 }; 630 631 pinctrl_hp: hpgrp { 632 fsl,pins = < 633 IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x31e 634 >; 635 }; 636 637 pinctrl_i3c2: i3c2grp { 638 fsl,pins = < 639 IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40000186 640 IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40000186 641 >; 642 }; 643 644 pinctrl_lpi2c1: lpi2c1grp { 645 fsl,pins = < 646 IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e 647 IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e 648 >; 649 }; 650 651 pinctrl_lpi2c2: lpi2c2grp { 652 fsl,pins = < 653 IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 654 IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 655 >; 656 }; 657 658 pinctrl_lpi2c3: lpi2c3grp { 659 fsl,pins = < 660 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 661 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 662 >; 663 }; 664 665 pinctrl_lpi2c4: lpi2c4grp { 666 fsl,pins = < 667 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 668 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 669 >; 670 }; 671 672 pinctrl_lpi2c6: lpi2c6grp { 673 fsl,pins = < 674 IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 675 IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 676 >; 677 }; 678 679 pinctrl_mipi_dsi_csi: mipidsigrp { 680 fsl,pins = < 681 IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x31e 682 >; 683 }; 684 685 pinctrl_pcal6524: pcal6524grp { 686 fsl,pins = < 687 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 688 >; 689 }; 690 691 pinctrl_pcie0: pcie0grp { 692 fsl,pins = < 693 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e 694 IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e 695 >; 696 }; 697 698 pinctrl_pdm: pdmgrp { 699 fsl,pins = < 700 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 701 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 702 >; 703 }; 704 705 pinctrl_ptn5110: ptn5110grp { 706 fsl,pins = < 707 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e 708 >; 709 }; 710 711 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 712 fsl,pins = < 713 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 714 >; 715 }; 716 717 pinctrl_sai1: sai1grp { 718 fsl,pins = < 719 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 720 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 721 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 722 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 723 >; 724 }; 725 726 pinctrl_sai2: sai2grp { 727 fsl,pins = < 728 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 729 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 730 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 731 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 732 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 733 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 734 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 735 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 736 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 737 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 738 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 739 >; 740 }; 741 742 pinctrl_sai3: sai3grp { 743 fsl,pins = < 744 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 745 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 746 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 747 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 748 IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x31e 749 >; 750 }; 751 752 pinctrl_spdif: spdifgrp { 753 fsl,pins = < 754 IMX95_PAD_GPIO_IO22__SPDIF_IN 0x3fe 755 IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x3fe 756 >; 757 }; 758 759 pinctrl_tpm3: tpm3grp { 760 fsl,pins = < 761 IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e 762 >; 763 }; 764 765 pinctrl_tpm6: tpm6grp { 766 fsl,pins = < 767 IMX95_PAD_GPIO_IO08__TPM6_CH0 0x51e 768 >; 769 }; 770 771 pinctrl_uart1: uart1grp { 772 fsl,pins = < 773 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 774 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 775 >; 776 }; 777 778 pinctrl_uart5: uart5grp { 779 fsl,pins = < 780 IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 781 IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e 782 IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 783 IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 784 >; 785 }; 786 787 pinctrl_usdhc1: usdhc1grp { 788 fsl,pins = < 789 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 790 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 791 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 792 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 793 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 794 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 795 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 796 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 797 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 798 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 799 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 800 >; 801 }; 802 803 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 804 fsl,pins = < 805 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 806 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 807 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 808 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 809 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 810 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 811 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 812 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 813 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 814 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 815 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 816 >; 817 }; 818 819 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 820 fsl,pins = < 821 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 822 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 823 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 824 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 825 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 826 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 827 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 828 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 829 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 830 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 831 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 832 >; 833 }; 834 835 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 836 fsl,pins = < 837 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 838 >; 839 }; 840 841 pinctrl_usdhc2: usdhc2grp { 842 fsl,pins = < 843 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 844 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 845 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 846 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 847 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 848 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 849 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 850 >; 851 }; 852 853 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 854 fsl,pins = < 855 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 856 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 857 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 858 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 859 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 860 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 861 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 862 >; 863 }; 864 865 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 866 fsl,pins = < 867 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 868 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 869 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 870 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 871 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 872 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 873 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 874 >; 875 }; 876 877 pinctrl_usdhc3: usdhc3grp { 878 fsl,pins = < 879 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 880 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 881 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 882 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 883 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 884 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 885 >; 886 }; 887 888 pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { 889 fsl,pins = < 890 IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e 891 >; 892 }; 893 894 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 895 fsl,pins = < 896 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 897 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 898 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 899 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 900 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 901 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 902 >; 903 }; 904 905 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 906 fsl,pins = < 907 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe 908 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe 909 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 910 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 911 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 912 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 913 >; 914 }; 915}; 916 917&scmi_misc { 918 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>, 919 <BRD_SM_CTRL_PCIE1_WAKE 1>, 920 <BRD_SM_CTRL_BT_WAKE 1>, 921 <BRD_SM_CTRL_PCIE2_WAKE 1>, 922 <BRD_SM_CTRL_BUTTON 1>; 923}; 924 925&thermal_zones { 926 a55-thermal { 927 cooling-maps { 928 map1 { 929 cooling-device = <&fan0 0 1>; 930 trip = <&atrip2>; 931 }; 932 933 map2 { 934 cooling-device = <&fan0 1 2>; 935 trip = <&atrip3>; 936 }; 937 938 map3 { 939 cooling-device = <&fan0 2 3>; 940 trip = <&atrip4>; 941 }; 942 }; 943 944 trips { 945 atrip2: trip2 { 946 hysteresis = <2000>; 947 temperature = <55000>; 948 type = "active"; 949 }; 950 951 atrip3: trip3 { 952 hysteresis = <2000>; 953 temperature = <65000>; 954 type = "active"; 955 }; 956 957 atrip4: trip4 { 958 hysteresis = <2000>; 959 temperature = <75000>; 960 type = "active"; 961 }; 962 }; 963 }; 964 965 pf09-thermal { 966 polling-delay = <2000>; 967 polling-delay-passive = <250>; 968 thermal-sensors = <&scmi_sensor 2>; 969 970 trips { 971 pf09_alert: trip0 { 972 hysteresis = <2000>; 973 temperature = <140000>; 974 type = "passive"; 975 }; 976 977 pf09_crit: trip1 { 978 hysteresis = <2000>; 979 temperature = <155000>; 980 type = "critical"; 981 }; 982 }; 983 }; 984 985 pf53arm-thermal { 986 polling-delay = <2000>; 987 polling-delay-passive = <250>; 988 thermal-sensors = <&scmi_sensor 4>; 989 990 cooling-maps { 991 map0 { 992 cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 993 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 994 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 995 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 996 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 997 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 998 trip = <&pf5301_alert>; 999 }; 1000 }; 1001 1002 trips { 1003 pf5301_alert: trip0 { 1004 hysteresis = <2000>; 1005 temperature = <140000>; 1006 type = "passive"; 1007 }; 1008 1009 pf5301_crit: trip1 { 1010 hysteresis = <2000>; 1011 temperature = <155000>; 1012 type = "critical"; 1013 }; 1014 }; 1015 }; 1016 1017 pf53soc-thermal { 1018 polling-delay = <2000>; 1019 polling-delay-passive = <250>; 1020 thermal-sensors = <&scmi_sensor 3>; 1021 1022 trips { 1023 pf5302_alert: trip0 { 1024 hysteresis = <2000>; 1025 temperature = <140000>; 1026 type = "passive"; 1027 }; 1028 1029 pf5302_crit: trip1 { 1030 hysteresis = <2000>; 1031 temperature = <155000>; 1032 type = "critical"; 1033 }; 1034 }; 1035 }; 1036}; 1037 1038&tpm3 { 1039 pinctrl-0 = <&pinctrl_tpm3>; 1040 pinctrl-names = "default"; 1041 status = "okay"; 1042}; 1043 1044&tpm6 { 1045 pinctrl-0 = <&pinctrl_tpm6>; 1046 pinctrl-names = "default"; 1047 status = "okay"; 1048}; 1049 1050&usb2 { 1051 dr_mode = "host"; 1052 vbus-supply = <®_usb_vbus>; 1053 disable-over-current; 1054 status = "okay"; 1055}; 1056 1057&usb3 { 1058 status = "okay"; 1059}; 1060 1061&usb3_dwc3 { 1062 adp-disable; 1063 dr_mode = "otg"; 1064 hnp-disable; 1065 role-switch-default-mode = "peripheral"; 1066 srp-disable; 1067 usb-role-switch; 1068 snps,dis-u1-entry-quirk; 1069 snps,dis-u2-entry-quirk; 1070 status = "okay"; 1071 1072 port { 1073 usb3_data_hs: endpoint { 1074 remote-endpoint = <&typec_con_hs>; 1075 }; 1076 }; 1077}; 1078 1079&usb3_phy { 1080 orientation-switch; 1081 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; 1082 fsl,phy-pcs-tx-swing-full-percent = <100>; 1083 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 1084 fsl,phy-tx-vboost-level-microvolt = <1156>; 1085 status = "okay"; 1086 1087 port { 1088 usb3_data_ss: endpoint { 1089 remote-endpoint = <&typec_con_ss>; 1090 }; 1091 }; 1092}; 1093 1094&usdhc1 { 1095 bus-width = <8>; 1096 non-removable; 1097 no-sd; 1098 no-sdio; 1099 pinctrl-0 = <&pinctrl_usdhc1>; 1100 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 1101 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1102 pinctrl-3 = <&pinctrl_usdhc1>; 1103 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 1104 fsl,tuning-step = <1>; 1105 status = "okay"; 1106}; 1107 1108&usdhc2 { 1109 bus-width = <4>; 1110 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 1111 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 1112 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 1113 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 1114 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 1115 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 1116 vmmc-supply = <®_usdhc2_vmmc>; 1117 fsl,tuning-step = <1>; 1118 status = "okay"; 1119}; 1120 1121&usdhc3 { 1122 bus-width = <4>; 1123 keep-power-in-suspend; 1124 mmc-pwrseq = <&usdhc3_pwrseq>; 1125 non-removable; 1126 pinctrl-0 = <&pinctrl_usdhc3>; 1127 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 1128 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 1129 pinctrl-3 = <&pinctrl_usdhc3>; 1130 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 1131 vmmc-supply = <®_usdhc3_vmmc>; 1132 wakeup-source; 1133 status = "okay"; 1134}; 1135 1136&wdog3 { 1137 status = "okay"; 1138}; 1139 1140&xcvr { 1141 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1142 <&scmi_clk IMX95_CLK_SPDIF>, 1143 <&dummy>, 1144 <&scmi_clk IMX95_CLK_AUDIOXCVR>, 1145 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1146 <&scmi_clk IMX95_CLK_AUDIOPLL2>; 1147 clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; 1148 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 1149 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 1150 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1151 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1152 <&scmi_clk IMX95_CLK_SPDIF>, 1153 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 1154 assigned-clock-parents = <0>, <0>, <0>, <0>, 1155 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1156 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1157 assigned-clock-rates = <3932160000>, <3612672000>, 1158 <393216000>, <361267200>, 1159 <12288000>, <0>; 1160 #sound-dai-cells = <0>; 1161 pinctrl-0 = <&pinctrl_spdif>; 1162 pinctrl-names = "default"; 1163 status = "okay"; 1164}; 1165