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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Drockchip-usb-phy.txt9 - #size-cells: should be 0
20 - #phy-cells: should be 0
22 "0x320" - for PHY attach to OTG controller
23 "0x334" - for PHY attach to HOST0 controller
24 "0x348" - for PHY attach to HOST1 controller
29 - #clock-cells: for users of the phy-pll, should be 0
45 #size-cells = <0>;
48 #phy-cells = <0>;
49 reg = <0x320>;
H A Drockchip-usb-phy.yaml7 title: Rockchip USB2.0 phy
23 const: 0
33 "usb-phy@[0-9a-f]+$":
41 const: 0
50 const: 0
72 #size-cells = <0>;
75 reg = <0x320>;
76 #phy-cells = <0>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dsamsung,amoled-mipi-dsi.yaml29 # Samsung S6E63J0X03 1.63" 320x320 AMOLED panel
62 #size-cells = <0>;
64 panel@0 {
66 reg = <0>;
69 reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx27-phytec-phycore-rdk.dts18 fsl,pcr = <0xf00080c0>;
35 de-active = <0>;
43 pinctrl-0 = <&pinctrl_csien>;
56 #phy-cells = <0>;
61 pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
68 pinctrl-0 = <&pinctrl_imxfb1>;
71 fsl,dmacr = <0x00020010>;
72 fsl,lscr1 = <0x00120300>;
73 fsl,lpccr = <0x00a903ff>;
80 pinctrl-0
[all...]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/freebsd/share/man/man4/
H A Dpcf.436 .Cd hint.pcf.0.at="isa"
37 .Cd hint.pcf.0.port="0x320"
38 .Cd hint.pcf.0.irq="5"
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_reg.h31 #define R92C_PCIE_MIO_INTF 0x0e4
32 #define R92C_PCIE_MIO_INTD 0x0e8
34 #define R92C_PCIE_CTRL_REG 0x300
35 #define R92C_INT_MIG 0x304
36 #define R92C_BCNQ_DESA 0x308
37 #define R92C_HQ_DESA 0x310
38 #define R92C_MGQ_DESA 0x318
39 #define R92C_VOQ_DESA 0x320
40 #define R92C_VIQ_DESA 0x328
41 #define R92C_BEQ_DESA 0x330
[all …]
/freebsd/sys/contrib/device-tree/src/arm/vt8500/
H A Dwm8650.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
43 reg = <0xd8140000 0x10000>;
52 reg = <0xD8150000 0x10000>;
58 reg = <0xd8110000 0x10000>;
67 reg = <0xd8130000 0x1000>;
71 #size-cells = <0>;
74 #clock-cells = <0>;
80 #clock-cells = <0>;
[all …]
H A Dwm8850.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
26 reg = <0x0 0x0>;
46 reg = <0xd8140000 0x10000>;
55 reg = <0xD8150000 0x10000>;
61 reg = <0xd8110000 0x10000>;
70 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
[all …]
H A Dwm8750.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
49 reg = <0xd8140000 0x10000>;
58 reg = <0xD8150000 0x10000>;
64 reg = <0xd8110000 0x10000>;
73 reg = <0xd8130000 0x1000>;
77 #size-cells = <0>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dpci.h17 #define RTK_PCI_CTRL 0x300
20 #define REG_DBI_WDATA_V1 0x03E8
21 #define REG_DBI_RDATA_V1 0x03EC
22 #define REG_DBI_FLAG_V1 0x03F0
28 #define REG_MDIO_V1 0x03F4
29 #define REG_PCIE_MIX_CFG 0x03F8
30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1 0
37 #define RTK_PCIE_LINK_CFG 0x0719
40 #define BIT_CLKREQ_N_PAD BIT(0)
[all...]
/freebsd/sys/dev/bhnd/bcma/
H A Dbcma_dmp.h47 (((_value) & _flag) != 0)
54 #define BCMA_OOB_BUSCONFIG 0x020
55 #define BCMA_OOB_STATUSA 0x100
56 #define BCMA_OOB_STATUSB 0x104
57 #define BCMA_OOB_STATUSC 0x108
58 #define BCMA_OOB_STATUSD 0x10c
59 #define BCMA_OOB_ENABLEA0 0x200
60 #define BCMA_OOB_ENABLEA1 0x204
61 #define BCMA_OOB_ENABLEA2 0x208
62 #define BCMA_OOB_ENABLEA3 0x20c
[all …]
/freebsd/sys/amd64/vmm/io/
H A Dvlapic_priv.h37 #define APIC_OFFSET_ID 0x20 /* Local APIC ID */
38 #define APIC_OFFSET_VER 0x30 /* Local APIC Version */
39 #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
40 #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
41 #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
42 #define APIC_OFFSET_EOI 0xB0 /* EOI Register */
43 #define APIC_OFFSET_RRR 0xC0 /* Remote read */
44 #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
45 #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
46 #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]

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