Lines Matching +full:0 +full:x320
37 #define APIC_OFFSET_ID 0x20 /* Local APIC ID */
38 #define APIC_OFFSET_VER 0x30 /* Local APIC Version */
39 #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
40 #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
41 #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
42 #define APIC_OFFSET_EOI 0xB0 /* EOI Register */
43 #define APIC_OFFSET_RRR 0xC0 /* Remote read */
44 #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
45 #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
46 #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
47 #define APIC_OFFSET_ISR0 0x100 /* In Service Register */
48 #define APIC_OFFSET_ISR1 0x110
49 #define APIC_OFFSET_ISR2 0x120
50 #define APIC_OFFSET_ISR3 0x130
51 #define APIC_OFFSET_ISR4 0x140
52 #define APIC_OFFSET_ISR5 0x150
53 #define APIC_OFFSET_ISR6 0x160
54 #define APIC_OFFSET_ISR7 0x170
55 #define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */
56 #define APIC_OFFSET_TMR1 0x190
57 #define APIC_OFFSET_TMR2 0x1A0
58 #define APIC_OFFSET_TMR3 0x1B0
59 #define APIC_OFFSET_TMR4 0x1C0
60 #define APIC_OFFSET_TMR5 0x1D0
61 #define APIC_OFFSET_TMR6 0x1E0
62 #define APIC_OFFSET_TMR7 0x1F0
63 #define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */
64 #define APIC_OFFSET_IRR1 0x210
65 #define APIC_OFFSET_IRR2 0x220
66 #define APIC_OFFSET_IRR3 0x230
67 #define APIC_OFFSET_IRR4 0x240
68 #define APIC_OFFSET_IRR5 0x250
69 #define APIC_OFFSET_IRR6 0x260
70 #define APIC_OFFSET_IRR7 0x270
71 #define APIC_OFFSET_ESR 0x280 /* Error Status Register */
72 #define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */
73 #define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */
74 #define APIC_OFFSET_ICR_HI 0x310
75 #define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */
76 #define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */
77 #define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */
78 #define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */
79 #define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */
80 #define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */
81 #define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */
82 #define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */
83 #define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */
84 #define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */
101 irrptr[0] = irrptr[0]; /* silence compiler */ \
102 VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \
103 VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \
104 VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \
105 VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \
106 VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \
107 VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \
108 VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \
109 VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \
110 } while (0)
115 isrptr[0] = isrptr[0]; /* silence compiler */ \
116 VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \
117 VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \
118 VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \
119 VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \
120 VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \
121 VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \
122 VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \
123 VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \
124 } while (0)