Lines Matching +full:0 +full:x320

17 #define RTK_PCI_CTRL		0x300
20 #define REG_DBI_WDATA_V1	0x03E8
21 #define REG_DBI_RDATA_V1	0x03EC
22 #define REG_DBI_FLAG_V1		0x03F0
28 #define REG_MDIO_V1		0x03F4
29 #define REG_PCIE_MIX_CFG	0x03F8
30 #define BITS_MDIO_ADDR_MASK	GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1	0
37 #define RTK_PCIE_LINK_CFG	0x0719
40 #define BIT_CLKREQ_N_PAD	BIT(0)
41 #define RTK_PCIE_CLKDLY_CTRL	0x0725
44 #define RTK_PCI_TXBD_DESA_BCNQ	0x308
45 #define RTK_PCI_TXBD_DESA_H2CQ	0x1320
46 #define RTK_PCI_TXBD_DESA_MGMTQ	0x310
47 #define RTK_PCI_TXBD_DESA_BKQ	0x330
48 #define RTK_PCI_TXBD_DESA_BEQ	0x328
49 #define RTK_PCI_TXBD_DESA_VIQ	0x320
50 #define RTK_PCI_TXBD_DESA_VOQ	0x318
51 #define RTK_PCI_TXBD_DESA_HI0Q	0x340
52 #define RTK_PCI_RXBD_DESA_MPDUQ	0x338
54 #define TRX_BD_IDX_MASK		GENMASK(11, 0)
58 #define RTK_PCI_TXBD_NUM_H2CQ	0x1328
59 #define RTK_PCI_TXBD_NUM_MGMTQ	0x380
60 #define RTK_PCI_TXBD_NUM_BKQ	0x38A
61 #define RTK_PCI_TXBD_NUM_BEQ	0x388
62 #define RTK_PCI_TXBD_NUM_VIQ	0x386
63 #define RTK_PCI_TXBD_NUM_VOQ	0x384
64 #define RTK_PCI_TXBD_NUM_HI0Q	0x38C
65 #define RTK_PCI_RXBD_NUM_MPDUQ	0x382
66 #define RTK_PCI_TXBD_IDX_H2CQ	0x132C
67 #define RTK_PCI_TXBD_IDX_MGMTQ	0x3B0
68 #define RTK_PCI_TXBD_IDX_BKQ	0x3AC
69 #define RTK_PCI_TXBD_IDX_BEQ	0x3A8
70 #define RTK_PCI_TXBD_IDX_VIQ	0x3A4
71 #define RTK_PCI_TXBD_IDX_VOQ	0x3A0
72 #define RTK_PCI_TXBD_IDX_HI0Q	0x3B8
73 #define RTK_PCI_RXBD_IDX_MPDUQ	0x3B4
75 #define RTK_PCI_TXBD_RWPTR_CLR	0x39C
76 #define RTK_PCI_TXBD_H2CQ_CSR	0x1330
81 #define RTK_PCI_HIMR0		0x0B0
82 #define RTK_PCI_HISR0		0x0B4
83 #define RTK_PCI_HIMR1		0x0B8
84 #define RTK_PCI_HISR1		0x0BC
85 #define RTK_PCI_HIMR2		0x10B0
86 #define RTK_PCI_HISR2		0x10B4
87 #define RTK_PCI_HIMR3		0x10B8
88 #define RTK_PCI_HISR3		0x10BC
89 /* IMR 0 */
114 #define IMR_ROK			BIT(0)
163 #define RTK_PCI_TXBD_BCN_WORK	0x383