Lines Matching +full:0 +full:x320
31 #define R92C_PCIE_MIO_INTF 0x0e4
32 #define R92C_PCIE_MIO_INTD 0x0e8
34 #define R92C_PCIE_CTRL_REG 0x300
35 #define R92C_INT_MIG 0x304
36 #define R92C_BCNQ_DESA 0x308
37 #define R92C_HQ_DESA 0x310
38 #define R92C_MGQ_DESA 0x318
39 #define R92C_VOQ_DESA 0x320
40 #define R92C_VIQ_DESA 0x328
41 #define R92C_BEQ_DESA 0x330
42 #define R92C_BKQ_DESA 0x338
43 #define R92C_RX_DESA 0x340
44 #define R92C_DBI 0x348
45 #define R92C_MDIO 0x354
46 #define R92C_DBG_SEL 0x360
47 #define R92C_PCIE_HRPWM 0x361
48 #define R92C_PCIE_HCPWM 0x363
49 #define R92C_UART_CTRL 0x364
50 #define R92C_UART_TX_DES 0x370
51 #define R92C_UART_RX_DES 0x378
54 #define R92C_GPIO_MUXCFG_RFKILL 0x0008
57 #define R92C_GPIO_IO_SEL_RFKILL 0x0008
60 #define R92C_LEDCFG2_EN 0x60
61 #define R92C_LEDCFG2_DIS 0x68
64 #define R92C_IMR_ROK 0x00000001 /* receive DMA OK */
65 #define R92C_IMR_VODOK 0x00000002 /* AC_VO DMA OK */
66 #define R92C_IMR_VIDOK 0x00000004 /* AC_VI DMA OK */
67 #define R92C_IMR_BEDOK 0x00000008 /* AC_BE DMA OK */
68 #define R92C_IMR_BKDOK 0x00000010 /* AC_BK DMA OK */
69 #define R92C_IMR_TXBDER 0x00000020 /* beacon transmit error */
70 #define R92C_IMR_MGNTDOK 0x00000040 /* management queue DMA OK */
71 #define R92C_IMR_TBDOK 0x00000080 /* beacon transmit OK */
72 #define R92C_IMR_HIGHDOK 0x00000100 /* high queue DMA OK */
73 #define R92C_IMR_BDOK 0x00000200 /* beacon queue DMA OK */
74 #define R92C_IMR_ATIMEND 0x00000400 /* ATIM window end interrupt */
75 #define R92C_IMR_RDU 0x00000800 /* Rx descriptor unavailable */
76 #define R92C_IMR_RXFOVW 0x00001000 /* receive FIFO overflow */
77 #define R92C_IMR_BCNINT 0x00002000 /* beacon DMA interrupt 0 */
78 #define R92C_IMR_PSTIMEOUT 0x00004000 /* powersave timeout */
79 #define R92C_IMR_TXFOVW 0x00008000 /* transmit FIFO overflow */
80 #define R92C_IMR_TIMEOUT1 0x00010000 /* timeout interrupt 1 */
81 #define R92C_IMR_TIMEOUT2 0x00020000 /* timeout interrupt 2 */
82 #define R92C_IMR_BCNDOK1 0x00040000 /* beacon queue DMA OK (1) */
83 #define R92C_IMR_BCNDOK2 0x00080000 /* beacon queue DMA OK (2) */
84 #define R92C_IMR_BCNDOK3 0x00100000 /* beacon queue DMA OK (3) */
85 #define R92C_IMR_BCNDOK4 0x00200000 /* beacon queue DMA OK (4) */
86 #define R92C_IMR_BCNDOK5 0x00400000 /* beacon queue DMA OK (5) */
87 #define R92C_IMR_BCNDOK6 0x00800000 /* beacon queue DMA OK (6) */
88 #define R92C_IMR_BCNDOK7 0x01000000 /* beacon queue DMA OK (7) */
89 #define R92C_IMR_BCNDOK8 0x02000000 /* beacon queue DMA OK (8) */
90 #define R92C_IMR_BCNDMAINT1 0x04000000 /* beacon DMA interrupt 1 */
91 #define R92C_IMR_BCNDMAINT2 0x08000000 /* beacon DMA interrupt 2 */
92 #define R92C_IMR_BCNDMAINT3 0x10000000 /* beacon DMA interrupt 3 */
93 #define R92C_IMR_BCNDMAINT4 0x20000000 /* beacon DMA interrupt 4 */
94 #define R92C_IMR_BCNDMAINT5 0x40000000 /* beacon DMA interrupt 5 */
95 #define R92C_IMR_BCNDMAINT6 0x80000000 /* beacon DMA interrupt 6 */