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/linux/Documentation/admin-guide/
H A Dparport.rst30 # insmod parport_pc io=0x3bc,0x378,0x278 irq=none,7,auto
33 0x3bc with no IRQ, one at 0x378 using IRQ 7, and one at 0x278 with an
49 options parport_pc io=0x378,0x278 irq=7,auto
51 modprobe will load ``parport_pc`` (with the options ``io=0x378,0x278 irq=7,auto``)
80 parport=0x3bc parport=0x378,7 parport=0x278,auto,nofifo
83 to add. Adding ``parport=0`` to the kernel command-line will disable
187 ``autoprobe[0-3]`` IEEE 1284 device ID information retrieved from
215 # insmod lp parport=0,2
226 name, so ``/dev/lp0`` was always the port at 0x3bc. This is no longer the
272 If that works fine, try with ``io=0x378 irq=7`` (adjust for your
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8135-apmixedsys.c38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
[all …]
H A Dclk-mt6735-apmixedsys.c14 #define AP_PLL_CON_5 0x014
15 #define ARMPLL_CON0 0x200
16 #define ARMPLL_CON1 0x204
17 #define ARMPLL_PWR_CON0 0x20c
18 #define MAINPLL_CON0 0x210
19 #define MAINPLL_CON1 0x214
20 #define MAINPLL_PWR_CON0 0x21c
21 #define UNIVPLL_CON0 0x220
22 #define UNIVPLL_CON1 0x224
23 #define UNIVPLL_PWR_CON0 0x22c
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap806.dtsi26 clocks = <&ap_clk 0>, <&ap_clk 1>;
28 reg = <0x278 0xa30>;
/linux/arch/arm/mach-rpc/include/mach/
H A Dio.h15 #define IO_SPACE_LIMIT 0xffff
19 * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7)
20 * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a)
/linux/Documentation/devicetree/bindings/cache/
H A Dstarfive,jh8100-starlink-cache.yaml59 reg = <0x0 0x15000000 0x0 0x278>;
63 cache-size = <0x400000>;
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/drivers/clk/mvebu/
H A Dap-cpu-clk.c22 #define AP806_CPU_CLUSTER0 0
25 #define APN806_CPU1_MASK 0x1
54 #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
55 #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
56 #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
57 #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
59 #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
60 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
61 #define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
63 (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_lrc.c31 #define LRC_VALID BIT_ULL(0)
92 * [5:0]: Number of NOPs or registers to set values to in case of
97 * is used for offsets smaller than 0x200 while the latter is for values bigger
102 * [6:0]: Register offset, without considering the engine base.
113 #define POSTED BIT(0) in set_offsets()
114 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
116 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
117 (((x) >> 2) & 0x7f) in set_offsets()
130 count = *data & 0x3f; in set_offsets()
142 u32 offset = 0; in set_offsets()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/linux/drivers/clk/meson/
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/linux/arch/arm/include/asm/
H A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
[all …]
/linux/Documentation/translations/zh_CN/dev-tools/
H A Dubsan.rst28 CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26
33 [<ffffffff815e6cd6>] dump_stack+0x45/0x5f
34 [<ffffffff8163a5ed>] ubsan_epilogue+0xd/0x40
35 [<ffffffff8163ac2b>] __ubsan_handle_shift_out_of_bounds+0xeb/0x130
36 [<ffffffff815f0001>] ? radix_tree_gang_lookup_slot+0x51/0x150
37 [<ffffffff8173c586>] _mix_pool_bytes+0x1e6/0x480
38 [<ffffffff83105653>] ? dmi_walk_early+0x48/0x5c
39 [<ffffffff8173c881>] add_device_randomness+0x61/0x130
40 [<ffffffff83105b35>] ? dmi_save_one_device+0xaa/0xaa
41 [<ffffffff83105653>] dmi_walk_early+0x48/0x5c
[all …]
/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/linux/Documentation/dev-tools/
H A Dubsan.rst24 CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26
29 [<ffffffff815e6cd6>] dump_stack+0x45/0x5f
30 [<ffffffff8163a5ed>] ubsan_epilogue+0xd/0x40
31 [<ffffffff8163ac2b>] __ubsan_handle_shift_out_of_bounds+0xeb/0x130
32 [<ffffffff815f0001>] ? radix_tree_gang_lookup_slot+0x51/0x150
33 [<ffffffff8173c586>] _mix_pool_bytes+0x1e6/0x480
34 [<ffffffff83105653>] ? dmi_walk_early+0x48/0x5c
35 [<ffffffff8173c881>] add_device_randomness+0x61/0x130
36 [<ffffffff83105b35>] ? dmi_save_one_device+0xaa/0xaa
37 [<ffffffff83105653>] dmi_walk_early+0x48/0x5c
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/
H A Drtl818x.h21 __le32 MAR[2]; /* 0x8 */
24 u8 rf_sw_config; /* 0x8 */
26 __le32 TMGDA; /* 0xc */
30 union { /* 0x10 */
41 __le32 TBEDA; /* 0x14 - for rtl8187se */
45 union { /* 0x20 */
50 union { /* 0x24 */
56 __le32 THPDA; /* 0x28 */
58 union { /* 0x2c */
67 u8 BSSID[6]; /* 0x2e */
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/linux/arch/powerpc/platforms/chrp/
H A Dpegasos_eth.c20 #define PEGASOS2_MARVELL_REGBASE (0xf1000000)
21 #define PEGASOS2_MARVELL_REGSIZE (0x00004000)
22 #define PEGASOS2_SRAM_BASE (0xf2000000)
33 #define MV64340_BASE_ADDR_ENABLE 0x278
34 #define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
35 #define MV64340_SRAM_CONFIG 0x380
38 [0] = {
40 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
41 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
49 .id = 0,
[all …]
/linux/drivers/mfd/
H A Ddb8500-prcmu-regs.h17 #define PRCM_ACLK_MGT (0x004)
18 #define PRCM_SVAMMCSPCLK_MGT (0x008)
19 #define PRCM_SIAMMDSPCLK_MGT (0x00C)
20 #define PRCM_SGACLK_MGT (0x014)
21 #define PRCM_UARTCLK_MGT (0x018)
22 #define PRCM_MSP02CLK_MGT (0x01C)
23 #define PRCM_I2CCLK_MGT (0x020)
24 #define PRCM_SDMMCCLK_MGT (0x024)
25 #define PRCM_SLIMCLK_MGT (0x028)
26 #define PRCM_PER1CLK_MGT (0x02C)
[all …]
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt14 SYSTEM CONTROLLER 0
24 - 0: reference clock of CPU cluster 0
51 mpp0 0 gpio, sdio(clk), spi0(clk)
91 reg = <0x6f4000 0x1000>;
104 offset = <0x1040>;
108 gpio-ranges = <&ap_pinctrl 0 0 19>;
109 marvell,pwm-offset = <0x10c0>;
146 reg = <0x6f8000 0x1000>;
150 reg = <0x80 0x10>;
177 reg = <0x6f8000 0x1000>;
[all …]

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