Lines Matching +full:0 +full:x278
22 #define AP806_CPU_CLUSTER0 0
25 #define APN806_CPU1_MASK 0x1
54 #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
55 #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
56 #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
57 #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
59 #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
60 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
61 #define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
63 (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
66 (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
68 #define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
92 #define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
93 #define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
94 #define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
95 #define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
98 (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
101 (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
103 #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
105 (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
179 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0. in ap_cpu_clk_set_rate()
208 BIT(clk->pll_regs->ratio_offset), 0); in ap_cpu_clk_set_rate()
210 return 0; in ap_cpu_clk_set_rate()
231 int ret, nclusters = 0, cluster_index = 0; in ap_cpu_clock_probe()
257 cpu = of_get_cpu_hwid(dn, 0); in ap_cpu_clock_probe()
286 char *clk_name = "cpu-cluster-0"; in ap_cpu_clock_probe()
292 cpu = of_get_cpu_hwid(dn, 0); in ap_cpu_clock_probe()