31 #define LRC_VALID				BIT_ULL(0)
92  * [5:0]: Number of NOPs or registers to set values to in case of
97  * is used for offsets smaller than 0x200 while the latter is for values bigger
102  * [6:0]: Register offset, without considering the engine base.
113 #define POSTED BIT(0)  in set_offsets()
114 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))  in set_offsets()
116 	(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \  in set_offsets()
117 	(((x) >> 2) & 0x7f)  in set_offsets()
130 		count = *data & 0x3f;  in set_offsets()
142 			u32 offset = 0;  in set_offsets()
151 			regs[0] = base + (offset << 2);  in set_offsets()
156 	*regs = MI_BATCH_BUFFER_END | BIT(0);  in set_offsets()
162 	REG16(0x244),
163 	REG(0x034),
164 	REG(0x030),
165 	REG(0x038),
166 	REG(0x03c),
167 	REG(0x168),
168 	REG(0x140),
169 	REG(0x110),
170 	REG(0x1c0),
171 	REG(0x1c4),
172 	REG(0x1c8),
173 	REG(0x180),
174 	REG16(0x2b4),
178 	REG16(0x3a8),
179 	REG16(0x28c),
180 	REG16(0x288),
181 	REG16(0x284),
182 	REG16(0x280),
183 	REG16(0x27c),
184 	REG16(0x278),
185 	REG16(0x274),
186 	REG16(0x270),
188 	0
194 	REG16(0x244),
195 	REG(0x034),
196 	REG(0x030),
197 	REG(0x038),
198 	REG(0x03c),
199 	REG(0x168),
200 	REG(0x140),
201 	REG(0x110),
202 	REG(0x1c0),
203 	REG(0x1c4),
204 	REG(0x1c8),
205 	REG(0x180),
206 	REG16(0x2b4),
207 	REG(0x120),
208 	REG(0x124),
212 	REG16(0x3a8),
213 	REG16(0x28c),
214 	REG16(0x288),
215 	REG16(0x284),
216 	REG16(0x280),
217 	REG16(0x27c),
218 	REG16(0x278),
219 	REG16(0x274),
220 	REG16(0x270),
222 	0
228 	REG16(0x244),
229 	REG(0x034),
230 	REG(0x030),
231 	REG(0x038),
232 	REG(0x03c),
233 	REG(0x168),
234 	REG(0x140),
235 	REG(0x110),
236 	REG(0x1c0),
237 	REG(0x1c4),
238 	REG(0x1c8),
239 	REG(0x180),
240 	REG16(0x2b4),
244 	REG16(0x3a8),
245 	REG16(0x28c),
246 	REG16(0x288),
247 	REG16(0x284),
248 	REG16(0x280),
249 	REG16(0x27c),
250 	REG16(0x278),
251 	REG16(0x274),
252 	REG16(0x270),
255 	REG(0x1b0),
256 	REG16(0x5a8),
257 	REG16(0x5ac),
260 	LRI(1, 0),
261 	REG(0x0c8),
265 	REG16(0x588),
266 	REG16(0x588),
267 	REG16(0x588),
268 	REG16(0x588),
269 	REG16(0x588),
270 	REG16(0x588),
271 	REG(0x028),
272 	REG(0x09c),
273 	REG(0x0c0),
274 	REG(0x178),
275 	REG(0x17c),
276 	REG16(0x358),
277 	REG(0x170),
278 	REG(0x150),
279 	REG(0x154),
280 	REG(0x158),
281 	REG16(0x41c),
282 	REG16(0x600),
283 	REG16(0x604),
284 	REG16(0x608),
285 	REG16(0x60c),
286 	REG16(0x610),
287 	REG16(0x614),
288 	REG16(0x618),
289 	REG16(0x61c),
290 	REG16(0x620),
291 	REG16(0x624),
292 	REG16(0x628),
293 	REG16(0x62c),
294 	REG16(0x630),
295 	REG16(0x634),
296 	REG16(0x638),
297 	REG16(0x63c),
298 	REG16(0x640),
299 	REG16(0x644),
300 	REG16(0x648),
301 	REG16(0x64c),
302 	REG16(0x650),
303 	REG16(0x654),
304 	REG16(0x658),
305 	REG16(0x65c),
306 	REG16(0x660),
307 	REG16(0x664),
308 	REG16(0x668),
309 	REG16(0x66c),
310 	REG16(0x670),
311 	REG16(0x674),
312 	REG16(0x678),
313 	REG16(0x67c),
314 	REG(0x068),
315 	REG(0x084),
318 	0
324 	REG16(0x244),
325 	REG(0x034),
326 	REG(0x030),
327 	REG(0x038),
328 	REG(0x03c),
329 	REG(0x168),
330 	REG(0x140),
331 	REG(0x110),
332 	REG(0x1c0),
333 	REG(0x1c4),
334 	REG(0x1c8),
335 	REG(0x180),
336 	REG16(0x2b4),
340 	REG16(0x3a8),
341 	REG16(0x28c),
342 	REG16(0x288),
343 	REG16(0x284),
344 	REG16(0x280),
345 	REG16(0x27c),
346 	REG16(0x278),
347 	REG16(0x274),
348 	REG16(0x270),
351 	REG(0x1b0),
352 	REG16(0x5a8),
353 	REG16(0x5ac),
356 	LRI(1, 0),
357 	REG(0x0c8),
359 	0
365 	REG16(0x244),
366 	REG(0x034),
367 	REG(0x030),
368 	REG(0x038),
369 	REG(0x03c),
370 	REG(0x168),
371 	REG(0x140),
372 	REG(0x110),
373 	REG(0x1c0),
374 	REG(0x1c4),
375 	REG(0x1c8),
376 	REG(0x180),
377 	REG16(0x2b4),
378 	REG(0x120),
379 	REG(0x124),
383 	REG16(0x3a8),
384 	REG16(0x28c),
385 	REG16(0x288),
386 	REG16(0x284),
387 	REG16(0x280),
388 	REG16(0x27c),
389 	REG16(0x278),
390 	REG16(0x274),
391 	REG16(0x270),
394 	REG(0x1b0),
395 	REG16(0x5a8),
396 	REG16(0x5ac),
399 	LRI(1, 0),
400 	REG(0x0c8),
402 	0
408 	REG16(0x244),
409 	REG(0x034),
410 	REG(0x030),
411 	REG(0x038),
412 	REG(0x03c),
413 	REG(0x168),
414 	REG(0x140),
415 	REG(0x110),
416 	REG(0x1c0),
417 	REG(0x1c4),
418 	REG(0x1c8),
419 	REG(0x180),
420 	REG16(0x2b4),
421 	REG(0x120),
422 	REG(0x124),
426 	REG16(0x3a8),
427 	REG16(0x28c),
428 	REG16(0x288),
429 	REG16(0x284),
430 	REG16(0x280),
431 	REG16(0x27c),
432 	REG16(0x278),
433 	REG16(0x274),
434 	REG16(0x270),
438 	REG16(0x5a8),
439 	REG16(0x5ac),
442 	LRI(1, 0),
443 	REG(0x0c8),
445 	0
449 	NOP(1),                 /* [0x00] */ \
450 	LRI(15, POSTED),        /* [0x01] */ \
451 	REG16(0x244),           /* [0x02] CTXT_SR_CTL */ \
452 	REG(0x034),             /* [0x04] RING_BUFFER_HEAD */ \
453 	REG(0x030),             /* [0x06] RING_BUFFER_TAIL */ \
454 	REG(0x038),             /* [0x08] RING_BUFFER_START */ \
455 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */ \
456 	REG(0x168),             /* [0x0c] BB_ADDR_UDW */ \
457 	REG(0x140),             /* [0x0e] BB_ADDR */ \
458 	REG(0x110),             /* [0x10] BB_STATE */ \
459 	REG(0x1c0),             /* [0x12] BB_PER_CTX_PTR */ \
460 	REG(0x1c4),             /* [0x14] RCS_INDIRECT_CTX */ \
461 	REG(0x1c8),             /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
462 	REG(0x180),             /* [0x18] CCID */ \
463 	REG16(0x2b4),           /* [0x1a] SEMAPHORE_TOKEN */ \
464 	REG(0x120),             /* [0x1c] PRT_BB_STATE */ \
465 	REG(0x124),             /* [0x1e] PRT_BB_STATE_UDW */ \
467 	NOP(1),                 /* [0x20] */ \
468 	LRI(9, POSTED),         /* [0x21] */ \
469 	REG16(0x3a8),           /* [0x22] CTX_TIMESTAMP */ \
470 	REG16(0x3ac),           /* [0x24] CTX_TIMESTAMP_UDW */ \
471 	REG(0x108),             /* [0x26] INDIRECT_RING_STATE */ \
472 	REG16(0x284),           /* [0x28] dummy reg */ \
473 	REG16(0x280),           /* [0x2a] CS_ACC_CTR_THOLD */ \
474 	REG16(0x27c),           /* [0x2c] CS_CTX_SYS_PASID */ \
475 	REG16(0x278),           /* [0x2e] CS_CTX_ASID */ \
476 	REG16(0x274),           /* [0x30] PTBP_UDW */ \
477 	REG16(0x270)            /* [0x32] PTBP_LDW */
482 	NOP(2),                 /* [0x34] */
483 	LRI(2, POSTED),         /* [0x36] */
484 	REG16(0x5a8),           /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
485 	REG16(0x5ac),           /* [0x39] PREEMPTION_STATUS */
487 	NOP(6),                 /* [0x41] */
488 	LRI(1, 0),              /* [0x47] */
489 	REG(0x0c8),             /* [0x48] R_PWR_CLK_STATE */
491 	0
497 	NOP(4 + 8 + 1),         /* [0x34] */
498 	LRI(2, POSTED),         /* [0x41] */
499 	REG16(0x200),           /* [0x42] BCS_SWCTRL */
500 	REG16(0x204),           /* [0x44] BLIT_CCTL */
502 	0
508 	0
512 	NOP(1),                 /* [0x00] */
513 	LRI(5, POSTED),         /* [0x01] */
514 	REG(0x034),             /* [0x02] RING_BUFFER_HEAD */
515 	REG(0x030),             /* [0x04] RING_BUFFER_TAIL */
516 	REG(0x038),             /* [0x06] RING_BUFFER_START */
517 	REG(0x048),             /* [0x08] RING_BUFFER_START_UDW */
518 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */
520 	NOP(5),                 /* [0x0c] */
521 	LRI(9, POSTED),         /* [0x11] */
522 	REG(0x168),             /* [0x12] BB_ADDR_UDW */
523 	REG(0x140),             /* [0x14] BB_ADDR */
524 	REG(0x110),             /* [0x16] BB_STATE */
525 	REG16(0x588),           /* [0x18] BB_STACK_WRITE_PORT */
526 	REG16(0x588),           /* [0x20] BB_STACK_WRITE_PORT */
527 	REG16(0x588),           /* [0x22] BB_STACK_WRITE_PORT */
528 	REG16(0x588),           /* [0x24] BB_STACK_WRITE_PORT */
529 	REG16(0x588),           /* [0x26] BB_STACK_WRITE_PORT */
530 	REG16(0x588),           /* [0x28] BB_STACK_WRITE_PORT */
532 	NOP(12),                 /* [0x00] */
534 	0
592 	regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;  in set_memory_based_intr()
597 	regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr;  in set_memory_based_intr()
599 	regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr;  in set_memory_based_intr()
608 		return 0x70;  in lrc_ring_mi_mode()
610 		return 0x60;  in lrc_ring_mi_mode()
629 	return 0;  in __xe_lrc_ring_offset()
786 		return 0;  in xe_lrc_indirect_ring_ggtt_addr()
874 #define PVC_CTX_ASID		(0x2e + 1)
875 #define PVC_CTX_ACC_CTR_THOLD	(0x2a + 1)
890 	lrc->flags = 0;  in xe_lrc_init()
910 	lrc->ring.tail = 0;  in xe_lrc_init()
911 	lrc->ctx_timestamp = 0;  in xe_lrc_init()
930 		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */  in xe_lrc_init()
935 		xe_map_memcpy_to(xe, &map, 0, init_data,  in xe_lrc_init()
953 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0);  in xe_lrc_init()
954 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0);  in xe_lrc_init()
960 		xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0);  in xe_lrc_init()
966 	xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0);  in xe_lrc_init()
995 	return 0;  in xe_lrc_init()
1036  * Called when ref == 0, release resources held by the Logical Ring Context
1094 	xe_map_memcpy_to(xe, &ring, 0, data, size);  in __xe_lrc_write_ring()
1208 	    GFXPIPE_SINGLE_DW_CMD(0, 0))  in instr_dw()
1215 	/* Most instructions have the # of dwords (minus 2) in 7:0 */  in instr_dw()
1267 			   dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "",  in dump_mi_command()
1268 			   dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : "");  in dump_mi_command()
1484 	while (remaining_dw > 0) {  in xe_lrc_dump_default()
1566 	int state_table_size = 0;  in xe_lrc_emit_hwe_state_instructions()
1572 	 * setting up the default LRC, the context switch will write 0's  in xe_lrc_emit_hwe_state_instructions()
1599 	for (int i = 0; i < state_table_size; i++) {  in xe_lrc_emit_hwe_state_instructions()
1605 		xe_gt_assert(gt, num_dw != 0);  in xe_lrc_emit_hwe_state_instructions()
1694 	drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc);  in xe_lrc_snapshot_print()
1695 	drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n",  in xe_lrc_snapshot_print()
1702 	drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp);  in xe_lrc_snapshot_print()
1703 	drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp);  in xe_lrc_snapshot_print()
1708 	drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()
1710 	for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) {  in xe_lrc_snapshot_print()
1717 	drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()