Lines Matching +full:0 +full:x278

21 		__le32	MAR[2];  /* 0x8 */
24 			u8 rf_sw_config; /* 0x8 */
26 			__le32 TMGDA; /* 0xc */
30 	union { /*  0x10  */
41 	__le32 TBEDA; /* 0x14 - for rtl8187se */
45 	union { /* 0x20 */
50 	union { /* 0x24 */
56 	__le32	THPDA; /* 0x28 */
58 	union { /* 0x2c */
67 	u8	BSSID[6]; /* 0x2e */
69 	union { /* 0x34 */
77 	u8	reserved_3[1]; /* 0x36 */
78 	u8	CMD; /* 0x37 */
82 	u8	reserved_4[4]; /* 0x38 */
89 		__le32	INT_STATUS_SE; /* 0x3c */
92 #define RTL818X_INT_RX_OK		(1 <<  0)
109 #define RTL818X_INT_SE_TIMER3		(1 <<  0)
135 	__le32	TX_CONF; /* 0x40 */
154 #define RTL818X_RX_CONF_MONITOR		(1 <<  0)
172 #define RTL818X_EEPROM_CMD_READ		(1 << 0)
176 #define RTL818X_EEPROM_CMD_NORMAL	(0 << 6)
186 #define RTL818X_MSR_NO_LINK		(0 << 2)
203 	__le32  IMR;		/* 0x6c	- Interrupt mask reg for 8187se */
230 #define IMR_TIMEOUT3	((1 << 0))	/* Time Out Interrupt 3 */
231 	__le16	BEACON_INTERVAL; /* 0x70 */
232 	__le16	ATIM_WND; /*  0x72 */
233 	__le16	BEACON_INTERVAL_TIME; /*  0x74 */
234 	__le16	ATIMTR_INTERVAL; /*  0x76 */
235 	u8	PHY_DELAY; /*  0x78 */
236 	u8	CARRIER_SENSE_COUNTER; /* 0x79 */
237 	u8	reserved_11[2]; /* 0x7a */
238 	u8	PHY[4]; /* 0x7c  */
239 	__le16	RFPinsOutput; /* 0x80 */
240 	__le16	RFPinsEnable; /* 0x82 */
241 	__le16	RFPinsSelect; /* 0x84 */
242 	__le16	RFPinsInput;  /* 0x86 */
243 	__le32	RF_PARA; /*  0x88 */
244 	__le32	RF_TIMING; /*  0x8c */
245 	u8	GP_ENABLE; /*  0x90 */
246 	u8	GPIO0; /*  0x91 */
247 	u8	GPIO1; /*  0x92 */
248 	u8	TPPOLL_STOP; /*  0x93 - rtl8187se only */
257 	__le32	HSSI_PARA; /*  0x94 */
258 	u8	reserved_13[4]; /* 0x98 */
259 	u8	TX_AGC_CTL; /*  0x9c */
260 #define RTL818X_TX_AGC_CTL_PERPACKET_GAIN	(1 << 0)
274 #define RTL818X_CW_CONF_PERPACKET_CW	(1 << 0)
290 #define RTL818X_R8187B_B	0
297 		__le16	ANAPARAM3; /* 0xee */
304 #define AC_PARAM_AIFS_SHIFT		0
306 	__le32 AC_VO_PARAM; /* 0xf0 */
308 	union { /* 0xf4 */
313 	union{ /* 0xf8 */
317 			__le16	TALLY_CNT; /* 0xfa */
322 		u8	TALLY_SEL; /* 0xfc */
338 #define FEMR_SE		REG_ADDR2(0x1D4)
339 #define ARFR		REG_ADDR2(0x1E0)
340 #define RFSW_CTRL	REG_ADDR2(0x272)
341 #define SW_3W_DB0	REG_ADDR2(0x274)
342 #define SW_3W_DB0_4	REG_ADDR4(0x274)
343 #define SW_3W_DB1	REG_ADDR2(0x278)
344 #define SW_3W_DB1_4	REG_ADDR4(0x278)
345 #define SW_3W_CMD1	REG_ADDR1(0x27D)
346 #define PI_DATA_REG	REG_ADDR2(0x360)
347 #define SI_DATA_REG     REG_ADDR2(0x362)