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Searched +full:0 +full:x259 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/mtd/maps/
H A Dsbc_gxx.c15 16 KiB memory window at 0xdc000-0xdffff
19 0x258
20 bit 0-7: address bit 14-21
21 0x259
22 bit 0-1: address bit 22-23
23 bit 7: 0 - reset/powered down
48 #define WINDOW_START 0xdc000
56 #define PAGE_IO 0x258
59 /* bit 7 of 0x259 must be 1 to enable device. */
60 #define DEVICE_ENABLE 0x8000
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/linux/drivers/usb/serial/
H A Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
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/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x00
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
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/linux/drivers/media/usb/gspca/
H A Dstk1135.c51 if (gspca_dev->usb_err < 0) in reg_r()
52 return 0; in reg_r()
53 ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), in reg_r()
54 0x00, in reg_r()
56 0x00, in reg_r()
61 gspca_dbg(gspca_dev, D_USBI, "reg_r 0x%x=0x%02x\n", in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
63 if (ret < 0) { in reg_r()
64 pr_err("reg_r 0x%x err %d\n", index, ret); in reg_r()
66 return 0; in reg_r()
[all …]
/linux/drivers/media/i2c/
H A Dmax96717.c23 #define MAX96717_DEVICE_ID 0xbf
24 #define MAX96717F_DEVICE_ID 0xc8
26 #define MAX96717_PAD_SINK 0
33 #define MAX96717_REG3 CCI_REG8(0x3)
34 #define MAX96717_RCLKSEL GENMASK(1, 0)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
40 #define MAX96717_DEV_REV_MASK GENMASK(3, 0)
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/linux/arch/x86/kernel/cpu/mce/
H A Damd.c30 #define THRESHOLD_MAX 0xFFF
31 #define INT_TYPE_APIC 0x00020000
32 #define MASK_VALID_HI 0x80000000
33 #define MASK_CNTP_HI 0x40000000
34 #define MASK_LOCKED_HI 0x20000000
35 #define MASK_LVTOFF_HI 0x00F00000
36 #define MASK_COUNT_EN_HI 0x00080000
37 #define MASK_INT_TYPE_HI 0x00060000
38 #define MASK_OVERFLOW_HI 0x00010000
39 #define MASK_ERR_COUNT_HI 0x00000FFF
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
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