Lines Matching +full:0 +full:x259
23 #define MAX96717_DEVICE_ID 0xbf
24 #define MAX96717F_DEVICE_ID 0xc8
26 #define MAX96717_PAD_SINK 0
33 #define MAX96717_REG3 CCI_REG8(0x3)
34 #define MAX96717_RCLKSEL GENMASK(1, 0)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
40 #define MAX96717_DEV_REV_MASK GENMASK(3, 0)
43 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110)
45 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112)
49 #define MAX96717_VTX0 CCI_REG8(0x24e)
50 #define MAX96717_VTX1 CCI_REG8(0x24f)
52 #define MAX96717_VTX_VS_DLY CCI_REG24(0x250)
53 #define MAX96717_VTX_VS_HIGH CCI_REG24(0x253)
54 #define MAX96717_VTX_VS_LOW CCI_REG24(0x256)
55 #define MAX96717_VTX_V2H CCI_REG24(0x259)
56 #define MAX96717_VTX_HS_HIGH CCI_REG16(0x25c)
57 #define MAX96717_VTX_HS_LOW CCI_REG16(0x25e)
58 #define MAX96717_VTX_HS_CNT CCI_REG16(0x260)
59 #define MAX96717_VTX_V2D CCI_REG24(0x262)
60 #define MAX96717_VTX_DE_HIGH CCI_REG16(0x265)
61 #define MAX96717_VTX_DE_LOW CCI_REG16(0x267)
62 #define MAX96717_VTX_DE_CNT CCI_REG16(0x269)
63 #define MAX96717_VTX29 CCI_REG8(0x26b)
64 #define MAX96717_VTX_MODE GENMASK(1, 0)
65 #define MAX96717_VTX_GRAD_INC CCI_REG8(0x26c)
66 #define MAX96717_VTX_CHKB_COLOR_A CCI_REG24(0x26d)
67 #define MAX96717_VTX_CHKB_COLOR_B CCI_REG24(0x270)
68 #define MAX96717_VTX_CHKB_RPT_CNT_A CCI_REG8(0x273)
69 #define MAX96717_VTX_CHKB_RPT_CNT_B CCI_REG8(0x274)
70 #define MAX96717_VTX_CHKB_ALT CCI_REG8(0x275)
74 #define MAX96717_GPIO_REG_A(gpio) CCI_REG8(0x2be + (gpio) * 3)
79 #define MAX96717_GPIO_OUT_DIS BIT(0)
83 #define MAX96717_FRONTOP0 CCI_REG8(0x308)
87 #define MAX96717_MIPI_RX1 CCI_REG8(0x331)
89 #define MAX96717_MIPI_RX2 CCI_REG8(0x332) /* phy1 Lanes map */
91 #define MAX96717_MIPI_RX3 CCI_REG8(0x333) /* phy2 Lanes map */
92 #define MAX96717_PHY1_LANES_MAP GENMASK(3, 0)
93 #define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */
95 #define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */
96 #define MAX96717_PHY2_LANES_POL GENMASK(2, 0)
99 #define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383)
103 #define REF_VTG0 CCI_REG8(0x3f0)
108 #define REFGEN_EN BIT(0)
111 #define PIO_SLEW_1 CCI_REG8(0x570)
114 MAX96717_VPG_DISABLED = 0,
149 return 0; in max96717_i2c_mux_select()
155 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE, in max96717_i2c_mux_init()
160 return i2c_mux_add_adapter(priv->mux, 0, 0); in max96717_i2c_mux_init()
167 start ? MAX96717_START_PORT_B : 0, NULL); in max96717_start_csi()
185 int ret = 0; in max96717_apply_patgen_timing()
192 MAX96717_PATTERN_CLK_FREQ, 0xa, &ret); in max96717_apply_patgen_timing()
197 cci_write(priv->regmap, MAX96717_VTX_VS_DLY, 0, &ret); in max96717_apply_patgen_timing()
212 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_A, 0xfecc00, &ret); in max96717_apply_patgen_timing()
214 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_B, 0x006aa7, &ret); in max96717_apply_patgen_timing()
215 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_A, 0x3c, &ret); in max96717_apply_patgen_timing()
216 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_B, 0x3c, &ret); in max96717_apply_patgen_timing()
217 cci_write(priv->regmap, MAX96717_VTX_CHKB_ALT, 0x3c, &ret); in max96717_apply_patgen_timing()
218 cci_write(priv->regmap, MAX96717_VTX_GRAD_INC, 0x10, &ret); in max96717_apply_patgen_timing()
227 int ret = 0; in max96717_apply_patgen()
232 cci_write(priv->regmap, MAX96717_VTX0, priv->pattern ? 0xfb : 0, in max96717_apply_patgen()
260 priv->pattern ? 0 : MAX96717_VIDEO_AUTO_BPP, in max96717_s_ctrl()
269 priv->pattern ? 0 : MAX96717_TUN_MODE, &ret); in max96717_s_ctrl()
317 if (ret < 0) in max96717_gpio_get_direction()
330 value ? MAX96717_GPIO_OUT : 0, NULL); in max96717_gpio_direction_out()
347 int i, ret = 0; in max96717_gpiochip_probe()
363 for (i = 0; i < gc->ngpio; i++) in max96717_gpiochip_probe()
366 0, &ret); in max96717_gpiochip_probe()
377 return 0; in max96717_gpiochip_probe()
401 return 0; in _max96717_set_routing()
460 .sink_stream = 0, in max96717_init_state()
462 .source_stream = 0, in max96717_init_state()
476 u64 val = 0; in max96717_pipe_pclkdet()
491 return 0; in max96717_log_status()
525 return 0; in max96717_enable_streams()
566 return 0; in max96717_disable_streams()
605 if (ret < 0) { in max96717_notify_bound()
615 &priv->sd.entity, 0, in max96717_notify_bound()
619 dev_err(dev, "Unable to link %s:%u -> %s:0\n", in max96717_notify_bound()
625 return 0; in max96717_notify_bound()
640 MAX96717_PAD_SINK, 0, 0); in max96717_v4l2_notifier_register()
668 return 0; in max96717_v4l2_notifier_register()
686 0, 0, max96717_test_pattern); in max96717_subdev_init()
724 return 0; in max96717_subdev_init()
756 { 13500000, true, 0 }, { 19200000, false, 0 },
772 unsigned int i, idx = 0; in max96717_clk_find_best_index()
775 for (i = 0; i < ARRAY_SIZE(max96717_predef_freqs); i++) { in max96717_clk_find_best_index()
808 int ret = 0; in max96717_clk_set_rate()
828 return 0; in max96717_clk_set_rate()
843 cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 0, NULL); in max96717_clk_unprepare()
868 cci_update_bits(priv->regmap, PIO_SLEW_1, BIT(5) | BIT(4), 0, &ret); in max96717_register_clkout()
876 MAX96717_DEFAULT_CLKOUT_RATE, 0); in max96717_register_clkout()
877 if (ret < 0) in max96717_register_clkout()
891 return 0; in max96717_register_clkout()
901 unsigned long lanes_used = 0; in max96717_init_csi_lanes()
902 unsigned int nlanes, lane, val = 0; in max96717_init_csi_lanes()
913 for (lane = 0; lane < nlanes + 1; lane++) { in max96717_init_csi_lanes()
917 if (lane == 0) in max96717_init_csi_lanes()
934 for (lane = 0, val = 0; lane < nlanes; lane++) { in max96717_init_csi_lanes()
1005 MAX96717_PAD_SINK, 0, 0); in max96717_parse_dt()
1013 if (ret < 0) in max96717_parse_dt()
1023 return 0; in max96717_parse_dt()