23 #define MAX96714_DEVICE_ID  0xc9
24 #define MAX96714F_DEVICE_ID 0xca
26 #define MAX96714_PAD_SINK   0
31 #define MAX96714_REG13                 CCI_REG8(0x0d)
32 #define MAX96714_DEV_REV               CCI_REG8(0x0e)
33 #define MAX96714_DEV_REV_MASK          GENMASK(3, 0)
34 #define MAX96714_LINK_LOCK             CCI_REG8(0x13)
36 #define MAX96714_IO_CHK0               CCI_REG8(0x38)
37 #define MAX96714_PATTERN_CLK_FREQ      GENMASK(1, 0)
39 #define MAX96714_VIDEO_RX8             CCI_REG8(0x11a)
43 #define MAX96714_PATGEN_0              CCI_REG8(0x240)
44 #define MAX96714_PATGEN_1              CCI_REG8(0x241)
46 #define MAX96714_PATGEN_VS_DLY         CCI_REG24(0x242)
47 #define MAX96714_PATGEN_VS_HIGH        CCI_REG24(0x245)
48 #define MAX96714_PATGEN_VS_LOW         CCI_REG24(0x248)
49 #define MAX96714_PATGEN_V2H            CCI_REG24(0x24b)
50 #define MAX96714_PATGEN_HS_HIGH        CCI_REG16(0x24e)
51 #define MAX96714_PATGEN_HS_LOW         CCI_REG16(0x250)
52 #define MAX96714_PATGEN_HS_CNT         CCI_REG16(0x252)
53 #define MAX96714_PATGEN_V2D            CCI_REG24(0x254)
54 #define MAX96714_PATGEN_DE_HIGH        CCI_REG16(0x257)
55 #define MAX96714_PATGEN_DE_LOW         CCI_REG16(0x259)
56 #define MAX96714_PATGEN_DE_CNT         CCI_REG16(0x25b)
57 #define MAX96714_PATGEN_GRAD_INC       CCI_REG8(0x25d)
58 #define MAX96714_PATGEN_CHKB_COLOR_A   CCI_REG24(0x25e)
59 #define MAX96714_PATGEN_CHKB_COLOR_B   CCI_REG24(0x261)
60 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264)
61 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265)
62 #define MAX96714_PATGEN_CHKB_ALT       CCI_REG8(0x266)
64 #define MAX96714_BACKTOP25             CCI_REG8(0x320)
65 #define CSI_DPLL_FREQ_MASK             GENMASK(4, 0)
68 #define MAX96714_MIPI_PHY0             CCI_REG8(0x330)
70 #define MAX96714_MIPI_STDBY_N          CCI_REG8(0x332)
72 #define MAX96714_MIPI_LANE_MAP         CCI_REG8(0x333)
73 #define MAX96714_MIPI_POLARITY         CCI_REG8(0x335)
74 #define MAX96714_MIPI_POLARITY_MASK    GENMASK(5, 0)
77 #define MAX96714_MIPI_LANE_CNT         CCI_REG8(0x44a)
79 #define MAX96714_MIPI_TX52             CCI_REG8(0x474)
80 #define MAX96714_TUN_EN                BIT(0)
85 	MAX96714_VPG_DISABLED = 0,
134 			       MAX96714_MIPI_STDBY_MASK, 0, NULL);  in max96714_disable_tx_port()
161 	int ret = 0;  in max96714_apply_patgen_timing()
173 	cci_write(priv->regmap, MAX96714_PATGEN_VS_DLY, 0, &ret);  in max96714_apply_patgen_timing()
188 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_A, 0xfecc00, &ret);  in max96714_apply_patgen_timing()
190 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_COLOR_B, 0x006aa7, &ret);  in max96714_apply_patgen_timing()
191 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_A, 0x3c, &ret);  in max96714_apply_patgen_timing()
192 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_RPT_CNT_B, 0x3c, &ret);  in max96714_apply_patgen_timing()
193 	cci_write(priv->regmap, MAX96714_PATGEN_CHKB_ALT, 0x3c, &ret);  in max96714_apply_patgen_timing()
194 	cci_write(priv->regmap, MAX96714_PATGEN_GRAD_INC, 0x10, &ret);  in max96714_apply_patgen_timing()
203 	int ret = 0;  in max96714_apply_patgen()
208 	cci_write(priv->regmap, MAX96714_PATGEN_0, priv->pattern ? 0xfb : 0,  in max96714_apply_patgen()
235 			      priv->pattern ? MAX96714_FORCE_CSI_OUT : 0, NULL);  in max96714_s_ctrl()
240 			       priv->pattern ? 0 : MAX96714_TUN_EN, &ret);  in max96714_s_ctrl()
289 	return 0;  in max96714_enable_streams()
326 	return 0;  in max96714_disable_streams()
357 	return 0;  in max96714_set_fmt()
407 			.sink_stream = 0,  in max96714_init_state()
409 			.source_stream = 0,  in max96714_init_state()
433 	u64 val = 0;  in max96714_link_locked()
466 	u64 freq = 0;  in max96714_csi_status()
486 	return 0;  in max96714_log_status()
522 	if (ret < 0) {  in max96714_notify_bound()
542 	return 0;  in max96714_notify_bound()
557 		return 0;  in max96714_v4l2_notifier_register()
579 	return 0;  in max96714_v4l2_notifier_register()
594 			       0, 0, &priv->tx_link_freq);  in max96714_create_subdev()
599 				     0, 0, max96714_test_pattern);  in max96714_create_subdev()
636 	return 0;  in max96714_create_subdev()
665 	return 0;  in max96714_i2c_mux_select()
671 				  1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE,  in max96714_i2c_mux_init()
676 	return i2c_mux_add_adapter(priv->mux, 0, 0);  in max96714_i2c_mux_init()
682 	unsigned long lanes_used = 0;  in max96714_init_tx_port()
699 	val = 0;  in max96714_init_tx_port()
700 	for (lane = 0; lane < mipi->num_data_lanes + 1; lane++) {  in max96714_init_tx_port()
703 		if (lane == 0)  in max96714_init_tx_port()
718 	val = 0;  in max96714_init_tx_port()
719 	for (lane = 0; lane < mipi->num_data_lanes; lane++) {  in max96714_init_tx_port()
744 		return 0;  in max96714_rxport_enable_poc()
754 		return 0;  in max96714_rxport_disable_poc()
768 						    MAX96714_PAD_SOURCE, 0, 0);  in max96714_parse_dt_txport()
784 	priv->tx_link_freq = vep.link_frequencies[0];  in max96714_parse_dt_txport()
818 						    MAX96714_PAD_SINK, 0, 0);  in max96714_parse_dt_rxport()
841 	return 0;  in max96714_parse_dt_rxport()
862 		ret = 0;  in max96714_parse_dt()
877 		gpiod_set_value_cansleep(priv->pd_gpio, 0);  in max96714_enable_core_hw()
912 	return 0;  in max96714_enable_core_hw()
937 	return 0;  in max96714_get_hw_resources()
978 	return 0;  in max96714_probe()