33 #define THRESHOLD_MAX     0xFFF
34 #define INT_TYPE_APIC     0x00020000
35 #define MASK_VALID_HI     0x80000000
36 #define MASK_CNTP_HI      0x40000000
37 #define MASK_LOCKED_HI    0x20000000
38 #define MASK_LVTOFF_HI    0x00F00000
39 #define MASK_COUNT_EN_HI  0x00080000
40 #define MASK_INT_TYPE_HI  0x00060000
41 #define MASK_OVERFLOW_HI  0x00010000
42 #define MASK_ERR_COUNT_HI 0x00000FFF
43 #define MASK_BLKPTR_LO    0xFF000000
44 #define MCG_XBLK_ADDR     0xC0000400
47 #define MSR_CU_DEF_ERR		0xC0000410
48 #define MASK_DEF_LVTOFF		0x000000F0
49 #define MASK_DEF_INT_TYPE	0x00000006
50 #define DEF_LVT_OFF		0x2
51 #define DEF_INT_TYPE_APIC	0x2
56 #define SMCA_THR_LVT_OFF	0xF000
153 	{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0)	},
155 	/* ZN Core (HWID=0xB0) MCA types */
156 	{ SMCA_LS,	 HWID_MCATYPE(0xB0, 0x0)	},
157 	{ SMCA_LS_V2,	 HWID_MCATYPE(0xB0, 0x10)	},
158 	{ SMCA_IF,	 HWID_MCATYPE(0xB0, 0x1)	},
159 	{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2)	},
160 	{ SMCA_DE,	 HWID_MCATYPE(0xB0, 0x3)	},
161 	/* HWID 0xB0 MCATYPE 0x4 is Reserved */
162 	{ SMCA_EX,	 HWID_MCATYPE(0xB0, 0x5)	},
163 	{ SMCA_FP,	 HWID_MCATYPE(0xB0, 0x6)	},
164 	{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7)	},
167 	{ SMCA_CS,	 HWID_MCATYPE(0x2E, 0x0)	},
168 	{ SMCA_PIE,	 HWID_MCATYPE(0x2E, 0x1)	},
169 	{ SMCA_CS_V2,	 HWID_MCATYPE(0x2E, 0x2)	},
170 	{ SMCA_MA_LLC,	 HWID_MCATYPE(0x2E, 0x4)	},
173 	{ SMCA_UMC,	 HWID_MCATYPE(0x96, 0x0)	},
174 	{ SMCA_UMC_V2,	 HWID_MCATYPE(0x96, 0x1)	},
177 	{ SMCA_PB,	 HWID_MCATYPE(0x05, 0x0)	},
180 	{ SMCA_PSP,	 HWID_MCATYPE(0xFF, 0x0)	},
181 	{ SMCA_PSP_V2,	 HWID_MCATYPE(0xFF, 0x1)	},
184 	{ SMCA_SMU,	 HWID_MCATYPE(0x01, 0x0)	},
185 	{ SMCA_SMU_V2,	 HWID_MCATYPE(0x01, 0x1)	},
188 	{ SMCA_MP5,	 HWID_MCATYPE(0x01, 0x2)	},
191 	{ SMCA_MPDMA,	 HWID_MCATYPE(0x01, 0x3)	},
194 	{ SMCA_NBIO,	 HWID_MCATYPE(0x18, 0x0)	},
197 	{ SMCA_PCIE,	 HWID_MCATYPE(0x46, 0x0)	},
198 	{ SMCA_PCIE_V2,	 HWID_MCATYPE(0x46, 0x1)	},
200 	{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0)	},
201 	{ SMCA_NBIF,	 HWID_MCATYPE(0x6C, 0x0)	},
202 	{ SMCA_SHUB,	 HWID_MCATYPE(0x80, 0x0)	},
203 	{ SMCA_SATA,	 HWID_MCATYPE(0xA8, 0x0)	},
204 	{ SMCA_USB,	 HWID_MCATYPE(0xAA, 0x0)	},
205 	{ SMCA_USR_DP,	 HWID_MCATYPE(0x170, 0x0)	},
206 	{ SMCA_USR_CP,	 HWID_MCATYPE(0x180, 0x0)	},
207 	{ SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)	},
208 	{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)	},
209 	{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)	},
210 	{ SMCA_GMI_PHY,	 HWID_MCATYPE(0x269, 0x0)	},
283 		 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)  in smca_configure()
285 		high |= BIT(0);  in smca_configure()
294 		 * high portion of the MSR). OS should set this to 0x1 to enable  in smca_configure()
298 		if ((low & BIT(5)) && !((high >> 5) & 0x3))  in smca_configure()
316 	for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {  in smca_configure()
353 	case 0x00000413:  in bank4_names()
356 	case 0xc0000408:  in bank4_names()
359 	case 0xc0000409:  in bank4_names()
363 		WARN(1, "Funny MSR: 0x%08x\n", b->address);  in bank4_names()
388 	if (apic < 0) {  in lvt_off_valid()
390 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,  in lvt_off_valid()
392 		return 0;  in lvt_off_valid()
402 			return 0;  in lvt_off_valid()
405 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",  in lvt_off_valid()
407 		return 0;  in lvt_off_valid()
477 	if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,  in setup_APIC_mce_threshold()
478 					      APIC_EILVT_MSG_FIX, 0))  in setup_APIC_mce_threshold()
486 	if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,  in setup_APIC_deferred_error()
487 					      APIC_EILVT_MSG_FIX, 0))  in setup_APIC_deferred_error()
495 	u32 low = 0, high = 0;  in deferred_error_interrupt_enable()
503 		pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");  in deferred_error_interrupt_enable()
526 		return 0;  in smca_get_block_address()
535 	u32 addr = 0, offset = 0;  in get_block_address()
545 	case 0:  in get_block_address()
571 	memset(&b, 0, sizeof(b));  in prepare_threshold_block()
612 	if (c->x86 == 0x17 &&  in amd_filter_mce()
613 	    c->x86_model >= 0x10 && c->x86_model <= 0x2F &&  in amd_filter_mce()
614 	    bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)  in amd_filter_mce()
618 	if (c->x86 < 0x17) {  in amd_filter_mce()
619 		if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)  in amd_filter_mce()
628  * - MC4_MISC thresholding is not supported on Family 0x15.
629  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
630  *   Models 0x10-0x2F due to Erratum #1114.
639 	if (c->x86 == 0x15 && bank == 4) {  in disable_err_thresholding()
640 		msrs[0] = 0x00000413; /* MC4_MISC0 */  in disable_err_thresholding()
641 		msrs[1] = 0xc0000408; /* MC4_MISC1 */  in disable_err_thresholding()
643 	} else if (c->x86 == 0x17 &&  in disable_err_thresholding()
644 		   (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {  in disable_err_thresholding()
649 		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);  in disable_err_thresholding()
663 	for (i = 0; i < num_msrs; i++)  in disable_err_thresholding()
675 	u32 low = 0, high = 0, address = 0;  in mce_amd_feature_init()
679 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in mce_amd_feature_init()
685 		for (block = 0; block < NR_BLOCKS; ++block) {  in mce_amd_feature_init()
714 	return m->bank == 4 && XEC(m->status, 0x1f) == 8;  in legacy_mce_is_memory_error()
719  * Extended Error Code 0.
725 	if (XEC(m->status, 0x3f))  in smca_mce_is_memory_error()
825 	u64 status, addr = 0;  in _log_error_bank()
836 	wrmsrl(msr_stat, 0);  in _log_error_bank()
855 	wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);  in _log_error_deferred()
870 	if (_log_error_deferred(bank, 0))  in log_error_deferred()
878 			      MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);  in log_error_deferred()
886 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)  in amd_deferred_error_interrupt()
898 	u32 low = 0, high = 0;  in log_and_reset_block()
913 	memset(&tr, 0, sizeof(tr));  in log_and_reset_block()
936 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in amd_threshold_interrupt()
981 	if (kstrtoul(buf, 0, &new) < 0)  in SHOW_FIELDS()
986 	memset(&tr, 0, sizeof(tr));  in SHOW_FIELDS()
1001 	if (kstrtoul(buf, 0, &new) < 0)  in store_threshold_limit()
1009 	memset(&tr, 0, sizeof(tr));  in store_threshold_limit()
1133 		return 0;  in allocate_threshold_blocks()
1136 		return 0;  in allocate_threshold_blocks()
1142 			return 0;  in allocate_threshold_blocks()
1157 	b->interrupt_enable	= 0;  in allocate_threshold_blocks()
1182 		return 0;  in allocate_threshold_blocks()
1191 	return 0;  in allocate_threshold_blocks()
1206 	int err = 0;  in __threshold_add_blocks()
1232 	int err = 0;  in threshold_create_bank()
1281 	err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));  in threshold_create_bank()
1286 	return 0;  in threshold_create_bank()
1358 	for (bank = 0; bank < numbanks; bank++) {  in __threshold_remove_device()
1373 		return 0;  in mce_threshold_remove_device()
1382 	return 0;  in mce_threshold_remove_device()
1403 		return 0;  in mce_threshold_create_device()
1407 		return 0;  in mce_threshold_create_device()
1414 	for (bank = 0; bank < numbanks; ++bank) {  in mce_threshold_create_device()
1427 	return 0;  in mce_threshold_create_device()