Lines Matching +full:0 +full:x259
44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
74 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
76 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
78 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
80 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
81 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
82 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
87 #define DP_AUX_I2C_WRITE 0x0
88 #define DP_AUX_I2C_READ 0x1
89 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
90 #define DP_AUX_I2C_MOT 0x4
91 #define DP_AUX_NATIVE_WRITE 0x8
92 #define DP_AUX_NATIVE_READ 0x9
94 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
95 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
96 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
97 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
99 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
100 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
101 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
102 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
107 #define DP_DPCD_REV 0x000
108 # define DP_DPCD_REV_10 0x10
109 # define DP_DPCD_REV_11 0x11
110 # define DP_DPCD_REV_12 0x12
111 # define DP_DPCD_REV_13 0x13
112 # define DP_DPCD_REV_14 0x14
114 #define DP_MAX_LINK_RATE 0x001
116 #define DP_MAX_LANE_COUNT 0x002
117 # define DP_MAX_LANE_COUNT_MASK 0x1f
121 #define DP_MAX_DOWNSPREAD 0x003
122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
127 #define DP_NORP 0x004
129 #define DP_DOWNSTREAMPORT_PRESENT 0x005
130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
140 # define DP_CAP_ANSI_8B10B (1 << 0)
143 #define DP_DOWN_STREAM_PORT_COUNT 0x007
144 # define DP_PORT_COUNT_MASK 0x0f
148 #define DP_RECEIVE_PORT_0_CAP_0 0x008
153 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
155 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
156 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
158 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
159 # define DP_I2C_SPEED_1K 0x01
160 # define DP_I2C_SPEED_5K 0x02
161 # define DP_I2C_SPEED_10K 0x04
162 # define DP_I2C_SPEED_100K 0x08
163 # define DP_I2C_SPEED_400K 0x10
164 # define DP_I2C_SPEED_1M 0x20
166 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
167 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
171 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
172 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
175 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
176 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
179 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
183 #define DP_FAUX_CAP 0x020 /* 1.2 */
184 # define DP_FAUX_CAP_1 (1 << 0)
186 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
187 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
191 #define DP_MSTM_CAP 0x021 /* 1.2 */
192 # define DP_MST_CAP (1 << 0)
195 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
198 #define DP_AV_GRANULARITY 0x023
199 # define DP_AG_FACTOR_MASK (0xf << 0)
200 # define DP_AG_FACTOR_3MS (0 << 0)
201 # define DP_AG_FACTOR_2MS (1 << 0)
202 # define DP_AG_FACTOR_1MS (2 << 0)
203 # define DP_AG_FACTOR_500US (3 << 0)
204 # define DP_AG_FACTOR_200US (4 << 0)
205 # define DP_AG_FACTOR_100US (5 << 0)
206 # define DP_AG_FACTOR_10US (6 << 0)
207 # define DP_AG_FACTOR_1US (7 << 0)
208 # define DP_VG_FACTOR_MASK (0xf << 4)
209 # define DP_VG_FACTOR_3MS (0 << 4)
216 #define DP_AUD_DEC_LAT0 0x024
217 #define DP_AUD_DEC_LAT1 0x025
219 #define DP_AUD_PP_LAT0 0x026
220 #define DP_AUD_PP_LAT1 0x027
222 #define DP_VID_INTER_LAT 0x028
224 #define DP_VID_PROG_LAT 0x029
226 #define DP_REP_LAT 0x02a
228 #define DP_AUD_DEL_INS0 0x02b
229 #define DP_AUD_DEL_INS1 0x02c
230 #define DP_AUD_DEL_INS2 0x02d
233 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
234 # define DP_ALPM_CAP (1 << 0)
238 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
239 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
241 #define DP_GUID 0x030 /* 1.2 */
243 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
244 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
249 #define DP_DSC_REV 0x061
250 # define DP_DSC_MAJOR_MASK (0xf << 0)
251 # define DP_DSC_MINOR_MASK (0xf << 4)
252 # define DP_DSC_MAJOR_SHIFT 0
255 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
256 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
257 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
258 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
259 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
261 #define DP_DSC_RC_BUF_SIZE 0x063
263 #define DP_DSC_SLICE_CAP_1 0x064
264 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
272 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
273 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
274 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
275 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
276 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
277 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
278 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
279 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
280 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
281 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
282 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
284 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
285 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
288 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
290 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
291 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
292 # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */
295 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
296 # define DP_DSC_RGB (1 << 0)
302 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
307 #define DP_DSC_PEAK_THROUGHPUT 0x06B
308 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
310 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
311 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
314 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
315 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
316 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
317 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
318 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
319 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
320 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
321 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
322 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
323 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
324 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
325 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
326 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
328 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
345 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
349 #define DP_DSC_SLICE_CAP_2 0x06D
350 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
354 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
355 # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
356 # define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
357 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
358 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
359 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
360 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
361 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4
363 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
369 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
371 # define DP_PSR_SETUP_TIME_330 (0 << 1)
384 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
385 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
388 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
395 /* offset 0 */
396 #define DP_DOWNSTREAM_PORT_0 0x80
397 # define DP_DS_PORT_TYPE_MASK (7 << 0)
398 # define DP_DS_PORT_TYPE_DP 0
406 # define DP_DS_NON_EDID_MASK (0xf << 4)
416 # define DP_DS_MAX_BPC_MASK (3 << 0)
417 # define DP_DS_8BPC 0
423 # define DP_PCON_MAX_0GBPS (0 << 2)
436 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
453 #define DP_MAX_DOWNSTREAM_PORTS 0x10
456 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
457 # define DP_FEC_CAPABLE (1 << 0)
461 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
464 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
465 #define DP_PCON_DSC_ENCODER 0x092
466 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
470 #define DP_PCON_DSC_VERSION 0x093
471 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
472 # define DP_PCON_DSC_MINOR_MASK (0xF << 4)
473 # define DP_PCON_DSC_MAJOR_SHIFT 0
477 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
478 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
479 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0
485 #define DP_PCON_DSC_RC_BUF_SIZE 0x095
488 #define DP_PCON_DSC_SLICE_CAP_1 0x096
489 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
490 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
491 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
492 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
493 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
494 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
495 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
497 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
498 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
499 # define DP_PCON_DSC_DEPTH_9_BITS 0
509 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098
510 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
512 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
513 # define DP_PCON_DSC_ENC_RGB (0x1 << 0)
514 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
515 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
516 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
517 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
519 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
520 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
521 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
522 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
524 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
527 #define DP_PCON_DSC_SLICE_CAP_2 0x09C
528 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
529 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
530 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
533 #define DP_PCON_DSC_BPP_INCR 0x09E
534 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
535 # define DP_PCON_DSC_ONE_16TH_BPP 0
542 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
543 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
544 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
547 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
549 #define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */
550 # define DP_PANEL_REPLAY_SUPPORT (1 << 0)
554 #define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1
557 #define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2
558 #define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4
561 #define DP_LINK_BW_SET 0x100
562 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
563 # define DP_LINK_BW_1_62 0x06
564 # define DP_LINK_BW_2_7 0x0a
565 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
566 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
567 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
568 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
569 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
571 #define DP_LANE_COUNT_SET 0x101
572 # define DP_LANE_COUNT_MASK 0x0f
575 #define DP_TRAINING_PATTERN_SET 0x102
576 # define DP_TRAINING_PATTERN_DISABLE 0
582 # define DP_TRAINING_PATTERN_MASK 0x3
583 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
586 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
595 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
600 #define DP_TRAINING_LANE0_SET 0x103
601 #define DP_TRAINING_LANE1_SET 0x104
602 #define DP_TRAINING_LANE2_SET 0x105
603 #define DP_TRAINING_LANE3_SET 0x106
605 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
606 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
608 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
609 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
610 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
611 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
614 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
622 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
624 #define DP_DOWNSPREAD_CTRL 0x107
629 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
630 # define DP_SET_ANSI_8B10B (1 << 0)
633 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
636 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
637 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
641 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
642 #define DP_LINK_QUAL_LANE1_SET 0x10c
643 #define DP_LINK_QUAL_LANE2_SET 0x10d
644 #define DP_LINK_QUAL_LANE3_SET 0x10e
645 # define DP_LINK_QUAL_PATTERN_DISABLE 0
654 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
655 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
656 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
657 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
658 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
659 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
660 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
661 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
662 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48
663 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49
664 # define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a
665 # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b
667 #define DP_TRAINING_LANE0_1_SET2 0x10f
668 #define DP_TRAINING_LANE2_3_SET2 0x110
669 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
674 #define DP_MSTM_CTRL 0x111 /* 1.2 */
675 # define DP_MST_EN (1 << 0)
679 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
680 #define DP_AUDIO_DELAY1 0x113
681 #define DP_AUDIO_DELAY2 0x114
683 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
684 # define DP_LINK_RATE_SET_SHIFT 0
685 # define DP_LINK_RATE_SET_MASK (7 << 0)
687 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
688 # define DP_ALPM_ENABLE (1 << 0)
692 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
693 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
696 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
697 # define DP_PWR_NOT_NEEDED (1 << 0)
699 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
700 # define DP_FEC_READY (1 << 0)
702 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
707 # define DP_FEC_LANE_0_SELECT (0 << 4)
712 #define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
713 #define DP_SDP_CRC16_128B132B_EN BIT(0)
715 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
716 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
718 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
719 # define DP_DECOMPRESSION_EN (1 << 0)
721 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
723 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
724 # define DP_PSR_ENABLE BIT(0)
733 #define DP_ADAPTER_CTRL 0x1a0
734 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
736 #define DP_BRANCH_DEVICE_CTRL 0x1a1
737 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
739 #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */
740 # define DP_PANEL_REPLAY_ENABLE (1 << 0)
748 #define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */
749 # define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0)
753 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3)
756 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
757 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
758 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
761 #define DP_SINK_COUNT 0x200
763 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
766 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
767 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
775 #define DP_LANE0_1_STATUS 0x202
776 #define DP_LANE2_3_STATUS 0x203
777 # define DP_LANE_CR_DONE (1 << 0)
785 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
786 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
793 #define DP_SINK_STATUS 0x205
794 # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
799 #define DP_ADJUST_REQUEST_LANE0_1 0x206
800 #define DP_ADJUST_REQUEST_LANE2_3 0x207
801 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
802 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
803 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
805 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
807 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
811 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
812 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
813 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
816 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
817 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
818 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
819 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
821 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
823 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
826 #define DP_TEST_REQUEST 0x218
827 # define DP_TEST_LINK_TRAINING (1 << 0)
835 #define DP_TEST_LINK_RATE 0x219
836 # define DP_LINK_RATE_162 (0x6)
837 # define DP_LINK_RATE_27 (0xa)
839 #define DP_TEST_LANE_COUNT 0x220
841 #define DP_TEST_PATTERN 0x221
842 # define DP_NO_TEST_PATTERN 0x0
843 # define DP_COLOR_RAMP 0x1
844 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
845 # define DP_COLOR_SQUARE 0x3
847 #define DP_TEST_H_TOTAL_HI 0x222
848 #define DP_TEST_H_TOTAL_LO 0x223
850 #define DP_TEST_V_TOTAL_HI 0x224
851 #define DP_TEST_V_TOTAL_LO 0x225
853 #define DP_TEST_H_START_HI 0x226
854 #define DP_TEST_H_START_LO 0x227
856 #define DP_TEST_V_START_HI 0x228
857 #define DP_TEST_V_START_LO 0x229
859 #define DP_TEST_HSYNC_HI 0x22A
861 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
862 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
864 #define DP_TEST_VSYNC_HI 0x22C
866 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
867 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
869 #define DP_TEST_H_WIDTH_HI 0x22E
870 #define DP_TEST_H_WIDTH_LO 0x22F
872 #define DP_TEST_V_HEIGHT_HI 0x230
873 #define DP_TEST_V_HEIGHT_LO 0x231
875 #define DP_TEST_MISC0 0x232
876 # define DP_TEST_SYNC_CLOCK (1 << 0)
879 # define DP_COLOR_FORMAT_RGB (0 << 1)
882 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
885 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
889 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
895 #define DP_TEST_MISC1 0x233
896 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
899 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
901 #define DP_TEST_MISC0 0x232
903 #define DP_TEST_CRC_R_CR 0x240
904 #define DP_TEST_CRC_G_Y 0x242
905 #define DP_TEST_CRC_B_CB 0x244
907 #define DP_TEST_SINK_MISC 0x246
909 # define DP_TEST_COUNT_MASK 0xf
911 #define DP_PHY_TEST_PATTERN 0x248
912 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
913 # define DP_PHY_TEST_PATTERN_NONE 0x0
914 # define DP_PHY_TEST_PATTERN_D10_2 0x1
915 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
916 # define DP_PHY_TEST_PATTERN_PRBS7 0x3
917 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
918 # define DP_PHY_TEST_PATTERN_CP2520 0x5
920 #define DP_PHY_SQUARE_PATTERN 0x249
922 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
923 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
924 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
925 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
926 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
927 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
928 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
929 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
930 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
931 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
932 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
934 #define DP_TEST_RESPONSE 0x260
935 # define DP_TEST_ACK (1 << 0)
939 #define DP_TEST_EDID_CHECKSUM 0x261
941 #define DP_TEST_SINK 0x270
942 # define DP_TEST_SINK_START (1 << 0)
943 #define DP_TEST_AUDIO_MODE 0x271
944 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
945 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
946 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
947 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
948 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
949 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
950 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
951 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
952 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
954 #define DP_FEC_STATUS 0x280 /* 1.4 */
955 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
958 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
960 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
961 # define DP_FEC_ERROR_COUNT_MASK 0x7F
964 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
965 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
968 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
969 /* up to ID_SLOT_63 at 0x2ff */
972 #define DP_SOURCE_OUI 0x300
975 #define DP_SINK_OUI 0x400
978 #define DP_BRANCH_OUI 0x500
979 #define DP_BRANCH_ID 0x503
980 #define DP_BRANCH_REVISION_START 0x509
981 #define DP_BRANCH_HW_REV 0x509
982 #define DP_BRANCH_SW_REV 0x50A
985 #define DP_SET_POWER 0x600
986 # define DP_SET_POWER_D0 0x1
987 # define DP_SET_POWER_D3 0x2
988 # define DP_SET_POWER_MASK 0x3
989 # define DP_SET_POWER_D3_AUX_ON 0x5
992 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
993 # define DP_EDP_11 0x00
994 # define DP_EDP_12 0x01
995 # define DP_EDP_13 0x02
996 # define DP_EDP_14 0x03
997 # define DP_EDP_14a 0x04 /* eDP 1.4a */
998 # define DP_EDP_14b 0x05 /* eDP 1.4b */
1000 #define DP_EDP_GENERAL_CAP_1 0x701
1001 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
1010 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
1011 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
1020 #define DP_EDP_GENERAL_CAP_2 0x703
1021 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
1024 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
1025 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
1026 # define DP_EDP_X_REGION_CAP_SHIFT 0
1027 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
1030 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
1031 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
1037 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
1038 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
1039 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
1040 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
1041 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
1042 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
1050 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1051 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1053 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
1054 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1055 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1056 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1058 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1060 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1063 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1064 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1065 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1067 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1068 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1069 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1071 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1072 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1073 #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734
1075 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1076 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1078 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1079 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1080 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1084 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1085 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1086 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1087 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1090 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1091 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1093 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1094 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1098 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1099 # define RX_CAP_CHANGED (1 << 0)
1106 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1107 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
1111 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1112 # define DP_PSR_CAPS_CHANGE (1 << 0)
1114 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1115 # define DP_PSR_SINK_INACTIVE 0
1121 # define DP_PSR_SINK_STATE_MASK 0x07
1123 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1124 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1125 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1126 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1129 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1130 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1138 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1139 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1141 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1142 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1143 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1144 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1146 #define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/
1147 # define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0)
1151 #define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */
1152 # define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)
1159 #define DP_DP13_DPCD_REV 0x2200
1161 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1162 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1171 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */
1172 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0)
1173 # define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)
1174 # define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0)
1178 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1179 # define DP_UHBR10 (1 << 0)
1183 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1185 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1186 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1187 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1188 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1189 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1190 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1191 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1192 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1194 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1195 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1198 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1199 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1201 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1202 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1203 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1208 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
1209 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1213 #define DP_CEC_TUNNELING_CONTROL 0x3001
1214 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
1217 #define DP_CEC_RX_MESSAGE_INFO 0x3002
1218 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1219 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1225 #define DP_CEC_TX_MESSAGE_INFO 0x3003
1226 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1227 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1228 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1232 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1233 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1240 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1241 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1249 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1250 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1259 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1260 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1261 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1264 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1265 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1266 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1275 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1281 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1282 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1283 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1290 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1293 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1294 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1298 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1299 # define DP_PCON_HDMI_LINK_MODE (1 << 0)
1300 # define DP_PCON_HDMI_MODE_TMDS 0
1302 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1310 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1311 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1312 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1313 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1317 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1318 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1320 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1321 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1330 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1331 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1332 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1333 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1334 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1335 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1340 * Valid Offsets to be added to Base : 0-127
1342 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1345 * Offset-0 8LSBs of the Slice height.
1348 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1351 * Offset-0 8LSBs of the Slice width.
1354 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1357 * Offset-0 8LSBs of the bits_per_pixel.
1360 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1363 #define DP_AUX_HDCP_BKSV 0x68000
1364 #define DP_AUX_HDCP_RI_PRIME 0x68005
1365 #define DP_AUX_HDCP_AKSV 0x68007
1366 #define DP_AUX_HDCP_AN 0x6800C
1367 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1368 #define DP_AUX_HDCP_BCAPS 0x68028
1370 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
1371 #define DP_AUX_HDCP_BSTATUS 0x68029
1375 # define DP_BSTATUS_READY BIT(0)
1376 #define DP_AUX_HDCP_BINFO 0x6802A
1377 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
1378 #define DP_AUX_HDCP_AINFO 0x6803B
1381 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1382 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1383 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1384 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1385 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1386 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1387 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1388 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1389 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1390 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1391 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1392 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1393 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1394 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1395 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1396 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1397 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1398 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1399 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1400 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1401 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1402 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1403 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1404 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1405 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1406 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1409 #define DP_TUNNELING_OUI 0xe0000
1412 #define DP_TUNNELING_DEV_ID 0xe0003
1415 #define DP_TUNNELING_HW_REV 0xe0009
1417 #define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
1418 #define DP_TUNNELING_HW_REV_MINOR_SHIFT 0
1419 #define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
1421 #define DP_TUNNELING_SW_REV_MAJOR 0xe000a
1422 #define DP_TUNNELING_SW_REV_MINOR 0xe000b
1424 #define DP_TUNNELING_CAPABILITIES 0xe000d
1427 #define DP_TUNNELING_SUPPORT (1 << 0)
1429 #define DP_IN_ADAPTER_INFO 0xe000e
1433 #define DP_USB4_DRIVER_ID 0xe000f
1437 #define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020
1440 #define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021
1444 #define DP_BW_GRANULARITY 0xe0022
1445 #define DP_BW_GRANULARITY_MASK 0x3
1447 #define DP_ESTIMATED_BW 0xe0023
1448 #define DP_ALLOCATED_BW 0xe0024
1450 #define DP_TUNNELING_STATUS 0xe0025
1454 #define DP_BW_REQUEST_FAILED (1 << 0)
1456 #define DP_TUNNELING_MAX_LINK_RATE 0xe0028
1458 #define DP_TUNNELING_MAX_LANE_COUNT 0xe0029
1459 #define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f
1461 #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030
1465 #define DP_REQUEST_BW 0xe0031
1469 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1470 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1471 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1472 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1473 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1474 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1475 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1476 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1477 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1479 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1480 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1499 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1500 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1508 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1512 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1516 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1517 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1518 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1519 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1523 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1524 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1527 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1532 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1536 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1538 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1539 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1540 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1541 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1542 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1543 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1544 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1546 #define DP_OUI_PHY_REPEATER1 0xf003d /* 1.3 */
1550 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1551 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1559 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1563 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1564 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1566 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1568 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1571 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1572 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1591 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1599 #define DP_PEER_DEVICE_NONE 0x0
1600 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1601 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1602 #define DP_PEER_DEVICE_SST_SINK 0x3
1603 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1606 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1607 #define DP_LINK_ADDRESS 0x01
1608 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1609 #define DP_ENUM_PATH_RESOURCES 0x10
1610 #define DP_ALLOCATE_PAYLOAD 0x11
1611 #define DP_QUERY_PAYLOAD 0x12
1612 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1613 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1614 #define DP_REMOTE_DPCD_READ 0x20
1615 #define DP_REMOTE_DPCD_WRITE 0x21
1616 #define DP_REMOTE_I2C_READ 0x22
1617 #define DP_REMOTE_I2C_WRITE 0x23
1618 #define DP_POWER_UP_PHY 0x24
1619 #define DP_POWER_DOWN_PHY 0x25
1620 #define DP_SINK_EVENT_NOTIFY 0x30
1621 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1622 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1627 #define DP_SIDEBAND_REPLY_ACK 0x00
1628 #define DP_SIDEBAND_REPLY_NAK 0x01
1631 #define DP_NAK_WRITE_FAILURE 0x01
1632 #define DP_NAK_INVALID_READ 0x02
1633 #define DP_NAK_CRC_FAILURE 0x03
1634 #define DP_NAK_BAD_PARAM 0x04
1635 #define DP_NAK_DEFER 0x05
1636 #define DP_NAK_LINK_FAILURE 0x06
1637 #define DP_NAK_NO_RESOURCES 0x07
1638 #define DP_NAK_DPCD_FAIL 0x08
1639 #define DP_NAK_I2C_NAK 0x09
1640 #define DP_NAK_ALLOCATE_FAIL 0x0a
1648 #define DP_MST_PHYSICAL_PORT_0 0
1651 #define DP_LINK_CONSTANT_N_VALUE 0x8000
1654 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1655 #define DP_RECEIVER_CAP_SIZE 0xf
1656 #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
1662 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1663 #define DP_SDP_AUDIO_STREAM 0x02
1664 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1665 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1666 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1667 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1668 #define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */
1669 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1670 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1671 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1672 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1674 /* 0x80+ CEA-861 infoframe types */
1676 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
1682 * @HB2: Secondary Data Packet Specific header, Byte 0
1692 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1693 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1694 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1701 * db[0]: Stereo Interface
1702 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1703 * db[2]: CRC value bits 7:0 of the R or Cr component
1705 * db[4]: CRC value bits 7:0 of the G or Y component
1707 * db[6]: CRC value bits 7:0 of the B or Cb component
1711 * db[0] - db[15]: Reserved
1722 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1736 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1742 DP_PIXELFORMAT_RGB = 0,
1743 DP_PIXELFORMAT_YUV444 = 0x1,
1744 DP_PIXELFORMAT_YUV422 = 0x2,
1745 DP_PIXELFORMAT_YUV420 = 0x3,
1746 DP_PIXELFORMAT_Y_ONLY = 0x4,
1747 DP_PIXELFORMAT_RAW = 0x5,
1748 DP_PIXELFORMAT_RESERVED = 0x6,
1776 DP_COLORIMETRY_DEFAULT = 0,
1777 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1778 DP_COLORIMETRY_BT709_YCC = 0x1,
1779 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1780 DP_COLORIMETRY_XVYCC_601 = 0x2,
1781 DP_COLORIMETRY_OPRGB = 0x3,
1782 DP_COLORIMETRY_XVYCC_709 = 0x3,
1783 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1784 DP_COLORIMETRY_SYCC_601 = 0x4,
1785 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1786 DP_COLORIMETRY_OPYCC_601 = 0x5,
1787 DP_COLORIMETRY_BT2020_RGB = 0x6,
1788 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1789 DP_COLORIMETRY_BT2020_YCC = 0x7,
1803 DP_DYNAMIC_RANGE_VESA = 0,
1822 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1823 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1824 DP_CONTENT_TYPE_PHOTO = 0x02,
1825 DP_CONTENT_TYPE_VIDEO = 0x03,
1826 DP_CONTENT_TYPE_GAME = 0x04,
1830 DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
1831 DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
1832 DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
1833 DP_AS_SDP_FAVT_TRR_REACHED = 0x03