/linux/arch/arm/mach-mv78xx0/ |
H A D | mv78xx0.h | 17 * f0800000 PCIe #0 I/O space 29 * fee00000 f0800000 64K PCIe #0 I/O space 39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) 42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000 49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) 52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000) [all …]
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | mediatek,ufs.yaml | 57 reg = <0 0x11270000 0 0x2300>; 63 freq-table-hz = <0 0>;
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/ |
H A D | fw.h | 7 #define FW_8192C_SIZE 0x3000 8 #define FW_8192C_START_ADDRESS 0x1000 9 #define FW_8192C_END_ADDRESS 0x3FFF 14 ((_pfwhdr->signature&0xFFFF) == 0x2300 ||\ 15 (_pfwhdr->signature&0xFFFF) == 0x2301 ||\ 16 (_pfwhdr->signature&0xFFFF) == 0x2302) 18 #define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
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H A D | sw.c | 31 * 0 - Disable ASPM, in rtl8723e_init_aspm_vars() 41 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl8723e_init_aspm_vars() 44 rtlpci->const_hostpci_aspm_setting = 0x02; in rtl8723e_init_aspm_vars() 48 * 0 - Default, in rtl8723e_init_aspm_vars() 52 * set default to RTL8192CE:0 RTL8192SE:2 in rtl8723e_init_aspm_vars() 54 rtlpci->const_hwsw_rfoff_d3 = 0; in rtl8723e_init_aspm_vars() 59 * 0 - Not support ASPM, in rtl8723e_init_aspm_vars() 71 int err = 0; in rtl8723e_init_sw_vars() 79 rtlpriv->dm.dm_flag = 0; in rtl8723e_init_sw_vars() 81 rtlpriv->dm.thermalvalue = 0; in rtl8723e_init_sw_vars() [all …]
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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | dcore0_tpc0_eml_etf_regs.h | 23 #define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004 25 #define mmDCORE0_TPC0_EML_ETF_STS 0x200C 27 #define mmDCORE0_TPC0_EML_ETF_RRD 0x2010 29 #define mmDCORE0_TPC0_EML_ETF_RRP 0x2014 31 #define mmDCORE0_TPC0_EML_ETF_RWP 0x2018 33 #define mmDCORE0_TPC0_EML_ETF_TRG 0x201C 35 #define mmDCORE0_TPC0_EML_ETF_CTL 0x2020 37 #define mmDCORE0_TPC0_EML_ETF_RWD 0x2024 39 #define mmDCORE0_TPC0_EML_ETF_MODE 0x2028 41 #define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C [all …]
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/linux/arch/arm64/boot/dts/broadcom/stingray/ |
H A D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>; 11 bus-range = <0x0 0x1>; 16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; 20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ 21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ 22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */ 23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ 24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */ 25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ 26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */ [all …]
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/linux/drivers/gpu/drm/msm/adreno/ |
H A D | a2xx_gpu.c | 18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit() 42 OUT_RING(ring, 0x00000000); in a2xx_submit() 49 OUT_RING(ring, 0x80000000); in a2xx_submit() 58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init() 62 /* All fields present (bits 9:0) */ in a2xx_me_init() 63 OUT_RING(ring, 0x000003ff); in a2xx_me_init() 65 OUT_RING(ring, 0x00000000); in a2xx_me_init() 67 OUT_RING(ring, 0x00000000); in a2xx_me_init() 69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init() 70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init() [all …]
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/linux/drivers/regulator/ |
H A D | slg51000-regulator.h | 14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105 15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106 16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107 17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109 18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c 19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d 20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e 21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111 22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112 23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115 [all …]
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H A D | qcom_spmi-regulator.c | 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 [all …]
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/linux/drivers/mfd/ |
H A D | si476x-prop.c | 25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array() 38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range() 49 0x0000, in si476x_core_is_valid_property_a10() 50 0x0500, 0x0501, in si476x_core_is_valid_property_a10() 51 0x0600, in si476x_core_is_valid_property_a10() 52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10() 53 0x0718, in si476x_core_is_valid_property_a10() 54 0x1207, 0x1208, in si476x_core_is_valid_property_a10() 55 0x2007, in si476x_core_is_valid_property_a10() 56 0x2300, in si476x_core_is_valid_property_a10() [all …]
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/linux/drivers/media/radio/si4713/ |
H A D | si4713.h | 25 #define SI4713_PRODUCT_NUMBER 0x0D 41 #define SI4713_PWUP_FUNC_TX 0x02 42 #define SI4713_PWUP_FUNC_PATCH 0x0F 43 #define SI4713_PWUP_OPMOD_ANALOG 0x50 44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F 47 #define SI4713_CMD_POWER_UP 0x01 50 #define SI4713_CMD_GET_REV 0x10 53 #define SI4713_CMD_POWER_DOWN 0x11 57 #define SI4713_CMD_SET_PROPERTY 0x12 61 #define SI4713_CMD_GET_PROPERTY 0x13 [all …]
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/linux/drivers/net/ethernet/tehuti/ |
H A D | tn40_regs.h | 8 #define TN40_REGS_SIZE 0x10000 10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 11 #define TN40_REG_TXD_CFG1_0 0x4000 12 #define TN40_REG_TXD_CFG1_1 0x4004 13 #define TN40_REG_TXD_CFG1_2 0x4008 14 #define TN40_REG_TXD_CFG1_3 0x400C 16 #define TN40_REG_RXF_CFG1_0 0x4010 17 #define TN40_REG_RXF_CFG1_1 0x4014 18 #define TN40_REG_RXF_CFG1_2 0x4018 19 #define TN40_REG_RXF_CFG1_3 0x401C [all …]
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/linux/drivers/net/ethernet/cavium/thunder/ |
H A D | nic_reg.h | 13 #define NIC_PF_CFG (0x0000) 14 #define NIC_PF_STATUS (0x0010) 15 #define NIC_PF_INTR_TIMER_CFG (0x0030) 16 #define NIC_PF_BIST_STATUS (0x0040) 17 #define NIC_PF_SOFT_RESET (0x0050) 18 #define NIC_PF_TCP_TIMER (0x0060) 19 #define NIC_PF_BP_CFG (0x0080) 20 #define NIC_PF_RRM_CFG (0x0088) 21 #define NIC_PF_CQM_CFG (0x00A0) 22 #define NIC_PF_CNM_CF (0x00A8) [all …]
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/linux/arch/powerpc/include/asm/ |
H A D | spu.h | 23 #define MFC_PUT_CMD 0x20 24 #define MFC_PUTS_CMD 0x28 25 #define MFC_PUTR_CMD 0x30 26 #define MFC_PUTF_CMD 0x22 27 #define MFC_PUTB_CMD 0x21 28 #define MFC_PUTFS_CMD 0x2A 29 #define MFC_PUTBS_CMD 0x29 30 #define MFC_PUTRF_CMD 0x32 31 #define MFC_PUTRB_CMD 0x31 32 #define MFC_PUTL_CMD 0x24 [all …]
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | cik.c | 82 .max_level = 0, 143 return 0; in cik_query_video_codecs() 205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg() 216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg() 245 0xc200, 0xe0ffffff, 0xe0000000 250 0x31dc, 0xffffffff, 0x00000800, 251 0x31dd, 0xffffffff, 0x00000800, 252 0x31e6, 0xffffffff, 0x00007fbf, 253 0x31e7, 0xffffffff, 0x00007faf 258 0xcd5, 0x00000333, 0x00000333, [all …]
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/linux/drivers/gpu/drm/rockchip/ |
H A D | rockchip_vop_reg.h | 11 #define RK3288_REG_CFG_DONE 0x0000 12 #define RK3288_VERSION_INFO 0x0004 13 #define RK3288_SYS_CTRL 0x0008 14 #define RK3288_SYS_CTRL1 0x000c 15 #define RK3288_DSP_CTRL0 0x0010 16 #define RK3288_DSP_CTRL1 0x0014 17 #define RK3288_DSP_BG 0x0018 18 #define RK3288_MCU_CTRL 0x001c 19 #define RK3288_INTR_CTRL0 0x0020 20 #define RK3288_INTR_CTRL1 0x0024 [all …]
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H A D | cdn-dp-reg.h | 12 #define ADDR_IMEM 0x10000 13 #define ADDR_DMEM 0x20000 16 #define APB_CTRL 0 17 #define XT_INT_CTRL 0x04 18 #define MAILBOX_FULL_ADDR 0x08 19 #define MAILBOX_EMPTY_ADDR 0x0c 20 #define MAILBOX0_WR_DATA 0x10 21 #define MAILBOX0_RD_DATA 0x14 22 #define KEEP_ALIVE 0x18 23 #define VER_L 0x1c [all …]
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H A D | rockchip_drm_vop2.h | 14 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0) 16 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0) 22 #define WIN_FEATURE_AFBDC BIT(0) 50 * should be all none zero, 0 will be treat as invalid; 52 #define VOP2_PD_CLUSTER0 BIT(0) 214 #define RK3568_GRF_VO_CON1 0x0364 216 #define RK3588_GRF_SOC_CON1 0x0304 217 #define RK3588_GRF_VOP_CON2 0x08 218 #define RK3588_GRF_VO1_CON0 0x00 221 #define RK3568_REG_CFG_DONE 0x000 [all …]
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/linux/drivers/net/ethernet/realtek/ |
H A D | r8169_phy_config.c | 23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage() 25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage() 28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage() 34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param() 36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param() 37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param() 39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param() 45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param() 47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param() 48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param() [all …]
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/linux/drivers/media/usb/pwc/ |
H A D | pwc.h | 46 #define PWC_DEBUG_LEVEL_MODULE BIT(0) 74 } while (0) 86 #define PWC_TRACE(fmt, args...) do { } while(0) 87 #define PWC_DEBUG(level, fmt, args...) do { } while(0) 89 #define pwc_trace 0 97 #define FEATURE_MOTOR_PANTILT 0x0001 98 #define FEATURE_CODEC1 0x0002 99 #define FEATURE_CODEC2 0x0004 127 #define SET_LUM_CTL 0x01 128 #define GET_LUM_CTL 0x02 [all …]
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/linux/drivers/bus/ |
H A D | omap_l3_noc.h | 16 #define CUSTOM_ERROR 0x2 17 #define STANDARD_ERROR 0x0 18 #define INBAND_ERROR 0x0 19 #define L3_APPLICATION_ERROR 0x0 20 #define L3_DEBUG_ERROR 0x1 23 #define L3_TARG_STDERRLOG_MAIN 0x48 24 #define L3_TARG_STDERRLOG_HDR 0x4c 25 #define L3_TARG_STDERRLOG_MSTADDR 0x50 26 #define L3_TARG_STDERRLOG_INFO 0x58 27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c [all …]
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/linux/drivers/scsi/ |
H A D | qlogicpti.h | 11 #define SBUS_CFG1 0x006UL 12 #define SBUS_CTRL 0x008UL 13 #define SBUS_STAT 0x00aUL 14 #define SBUS_SEMAPHORE 0x00cUL 15 #define CMD_DMA_CTRL 0x022UL 16 #define DATA_DMA_CTRL 0x042UL 17 #define MBOX0 0x080UL 18 #define MBOX1 0x082UL 19 #define MBOX2 0x084UL 20 #define MBOX3 0x086UL [all …]
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/linux/drivers/net/wireless/mediatek/mt7601u/ |
H A D | regs.h | 12 #define MT_ASIC_VERSION 0x0000 14 #define MT76XX_REV_E3 0x22 15 #define MT76XX_REV_E4 0x33 17 #define MT_CMB_CTRL 0x0020 21 #define MT_EFUSE_CTRL 0x0024 22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) 30 #define MT_EFUSE_DATA_BASE 0x0028 33 #define MT_COEXCFG0 0x0040 34 #define MT_COEXCFG0_COEX_EN BIT(0) 36 #define MT_WLAN_FUN_CTRL 0x0080 [all …]
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/linux/arch/mips/include/asm/ |
H A D | cpu.h | 16 register 15, select 0) is defined in this (backwards compatible) way: 24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 28 #define PRID_OPT_MASK 0xff000000 34 #define PRID_COMP_MASK 0xff0000 36 #define PRID_COMP_LEGACY 0x000000 37 #define PRID_COMP_MIPS 0x010000 38 #define PRID_COMP_BROADCOM 0x020000 39 #define PRID_COMP_ALCHEMY 0x030000 40 #define PRID_COMP_SIBYTE 0x040000 41 #define PRID_COMP_SANDCRAFT 0x050000 [all …]
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/linux/drivers/clk/imx/ |
H A D | clk-imx93.c | 58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, 59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, 61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, 65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, 66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, 67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, [all …]
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