Lines Matching +full:0 +full:x2300
16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
42 #define PRID_COMP_NXP 0x060000
43 #define PRID_COMP_TOSHIBA 0x070000
44 #define PRID_COMP_LSI 0x080000
45 #define PRID_COMP_LEXRA 0x0b0000
46 #define PRID_COMP_NETLOGIC 0x0c0000
47 #define PRID_COMP_CAVIUM 0x0d0000
48 #define PRID_COMP_LOONGSON 0x140000
49 #define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */
50 #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */
51 #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
52 #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
60 #define PRID_IMP_MASK 0xff00
66 #define PRID_IMP_R2000 0x0100
67 #define PRID_IMP_AU1_REV1 0x0100
68 #define PRID_IMP_AU1_REV2 0x0200
69 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */
70 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */
71 #define PRID_IMP_R4000 0x0400
72 #define PRID_IMP_R6000A 0x0600
73 #define PRID_IMP_R10000 0x0900
74 #define PRID_IMP_R4300 0x0b00
75 #define PRID_IMP_VR41XX 0x0c00
76 #define PRID_IMP_R12000 0x0e00
77 #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
78 #define PRID_IMP_R8000 0x1000
79 #define PRID_IMP_PR4450 0x1200
80 #define PRID_IMP_R4600 0x2000
81 #define PRID_IMP_R4700 0x2100
82 #define PRID_IMP_TX39 0x2200
83 #define PRID_IMP_R4640 0x2200
84 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */
85 #define PRID_IMP_R5000 0x2300
86 #define PRID_IMP_TX49 0x2d00
87 #define PRID_IMP_SONIC 0x2400
88 #define PRID_IMP_MAGIC 0x2500
89 #define PRID_IMP_RM7000 0x2700
90 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
91 #define PRID_IMP_RM9000 0x3400
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
93 #define PRID_IMP_R5432 0x5400
94 #define PRID_IMP_R5500 0x5500
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
99 #define PRID_IMP_UNKNOWN 0xff00
105 #define PRID_IMP_QEMU_GENERIC 0x0000
106 #define PRID_IMP_4KC 0x8000
107 #define PRID_IMP_5KC 0x8100
108 #define PRID_IMP_20KC 0x8200
109 #define PRID_IMP_4KEC 0x8400
110 #define PRID_IMP_4KSC 0x8600
111 #define PRID_IMP_25KF 0x8800
112 #define PRID_IMP_5KE 0x8900
113 #define PRID_IMP_4KECR2 0x9000
114 #define PRID_IMP_4KEMPR2 0x9100
115 #define PRID_IMP_4KSD 0x9200
116 #define PRID_IMP_24K 0x9300
117 #define PRID_IMP_34K 0x9500
118 #define PRID_IMP_24KE 0x9600
119 #define PRID_IMP_74K 0x9700
120 #define PRID_IMP_1004K 0x9900
121 #define PRID_IMP_1074K 0x9a00
122 #define PRID_IMP_M14KC 0x9c00
123 #define PRID_IMP_M14KEC 0x9e00
124 #define PRID_IMP_INTERAPTIV_UP 0xa000
125 #define PRID_IMP_INTERAPTIV_MP 0xa100
126 #define PRID_IMP_PROAPTIV_UP 0xa200
127 #define PRID_IMP_PROAPTIV_MP 0xa300
128 #define PRID_IMP_P6600 0xa400
129 #define PRID_IMP_M5150 0xa700
130 #define PRID_IMP_P5600 0xa800
131 #define PRID_IMP_I6400 0xa900
132 #define PRID_IMP_M6250 0xab00
133 #define PRID_IMP_I6500 0xb000
139 #define PRID_IMP_SB1 0x0100
140 #define PRID_IMP_SB1A 0x1100
146 #define PRID_IMP_SR71000 0x0400
152 #define PRID_IMP_BMIPS32_REV4 0x4000
153 #define PRID_IMP_BMIPS32_REV8 0x8000
154 #define PRID_IMP_BMIPS3300 0x9000
155 #define PRID_IMP_BMIPS3300_ALT 0x9100
156 #define PRID_IMP_BMIPS3300_BUG 0x0000
157 #define PRID_IMP_BMIPS43XX 0xa000
158 #define PRID_IMP_BMIPS5000 0x5a00
159 #define PRID_IMP_BMIPS5200 0x5b00
161 #define PRID_REV_BMIPS4380_LO 0x0040
162 #define PRID_REV_BMIPS4380_HI 0x006f
168 #define PRID_IMP_CAVIUM_CN38XX 0x0000
169 #define PRID_IMP_CAVIUM_CN31XX 0x0100
170 #define PRID_IMP_CAVIUM_CN30XX 0x0200
171 #define PRID_IMP_CAVIUM_CN58XX 0x0300
172 #define PRID_IMP_CAVIUM_CN56XX 0x0400
173 #define PRID_IMP_CAVIUM_CN50XX 0x0600
174 #define PRID_IMP_CAVIUM_CN52XX 0x0700
175 #define PRID_IMP_CAVIUM_CN63XX 0x9000
176 #define PRID_IMP_CAVIUM_CN68XX 0x9100
177 #define PRID_IMP_CAVIUM_CN66XX 0x9200
178 #define PRID_IMP_CAVIUM_CN61XX 0x9300
179 #define PRID_IMP_CAVIUM_CNF71XX 0x9400
180 #define PRID_IMP_CAVIUM_CN78XX 0x9500
181 #define PRID_IMP_CAVIUM_CN70XX 0x9600
182 #define PRID_IMP_CAVIUM_CN73XX 0x9700
183 #define PRID_IMP_CAVIUM_CNF75XX 0x9800
189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
191 #define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
196 #define PRID_IMP_NETLOGIC_XLR732 0x0000
197 #define PRID_IMP_NETLOGIC_XLR716 0x0200
198 #define PRID_IMP_NETLOGIC_XLR532 0x0900
199 #define PRID_IMP_NETLOGIC_XLR308 0x0600
200 #define PRID_IMP_NETLOGIC_XLR532C 0x0800
201 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00
202 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00
203 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00
204 #define PRID_IMP_NETLOGIC_XLS608 0x8000
205 #define PRID_IMP_NETLOGIC_XLS408 0x8800
206 #define PRID_IMP_NETLOGIC_XLS404 0x8c00
207 #define PRID_IMP_NETLOGIC_XLS208 0x8e00
208 #define PRID_IMP_NETLOGIC_XLS204 0x8f00
209 #define PRID_IMP_NETLOGIC_XLS108 0xce00
210 #define PRID_IMP_NETLOGIC_XLS104 0xcf00
211 #define PRID_IMP_NETLOGIC_XLS616B 0x4000
212 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00
213 #define PRID_IMP_NETLOGIC_XLS416B 0x4400
214 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00
215 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00
216 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00
217 #define PRID_IMP_NETLOGIC_AU13XX 0x8000
219 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000
220 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100
221 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200
222 #define PRID_IMP_NETLOGIC_XLP9XX 0x1500
223 #define PRID_IMP_NETLOGIC_XLP5XX 0x1300
226 * Particular Revision values for bits 7:0 of the PRId register.
229 #define PRID_REV_MASK 0x00ff
232 * Definitions for 7:0 on legacy processors
235 #define PRID_REV_TX4927 0x0022
236 #define PRID_REV_TX4937 0x0030
237 #define PRID_REV_R4400 0x0040
238 #define PRID_REV_R3000A 0x0030
239 #define PRID_REV_R3000 0x0020
240 #define PRID_REV_R2000A 0x0010
241 #define PRID_REV_TX3912 0x0010
242 #define PRID_REV_TX3922 0x0030
243 #define PRID_REV_TX3927 0x0040
244 #define PRID_REV_VR4111 0x0050
245 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
246 #define PRID_REV_VR4121 0x0060
247 #define PRID_REV_VR4122 0x0070
248 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
249 #define PRID_REV_VR4130 0x0080
250 #define PRID_REV_34K_V1_0_2 0x0022
251 #define PRID_REV_LOONGSON1B 0x0020
252 #define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
253 #define PRID_REV_LOONGSON2E 0x0002
254 #define PRID_REV_LOONGSON2F 0x0003
255 #define PRID_REV_LOONGSON2K_R1_0 0x0000
256 #define PRID_REV_LOONGSON2K_R1_1 0x0001
257 #define PRID_REV_LOONGSON2K_R1_2 0x0002
258 #define PRID_REV_LOONGSON2K_R1_3 0x0003
259 #define PRID_REV_LOONGSON3A_R1 0x0005
260 #define PRID_REV_LOONGSON3B_R1 0x0006
261 #define PRID_REV_LOONGSON3B_R2 0x0007
262 #define PRID_REV_LOONGSON3A_R2_0 0x0008
263 #define PRID_REV_LOONGSON3A_R3_0 0x0009
264 #define PRID_REV_LOONGSON3A_R2_1 0x000c
265 #define PRID_REV_LOONGSON3A_R3_1 0x000d
279 * FPU implementation/revision register (CP1 control register 0).
282 * | 0 | Implementation | Revision |
284 * 31 16 15 8 7 0
287 #define FPIR_IMP_MASK 0xff00
289 #define FPIR_IMP_NONE 0x0000
338 #define MIPS_CPU_ISA_II 0x00000001
339 #define MIPS_CPU_ISA_III 0x00000002
340 #define MIPS_CPU_ISA_IV 0x00000004
341 #define MIPS_CPU_ISA_V 0x00000008
342 #define MIPS_CPU_ISA_M32R1 0x00000010
343 #define MIPS_CPU_ISA_M32R2 0x00000020
344 #define MIPS_CPU_ISA_M64R1 0x00000040
345 #define MIPS_CPU_ISA_M64R2 0x00000080
346 #define MIPS_CPU_ISA_M32R5 0x00000100
347 #define MIPS_CPU_ISA_M64R5 0x00000200
348 #define MIPS_CPU_ISA_M32R6 0x00000400
349 #define MIPS_CPU_ISA_M64R6 0x00000800
360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
428 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */
429 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
430 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
431 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
432 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
433 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
434 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
435 #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
436 #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
437 #define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
438 #define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
439 #define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */
440 #define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */
441 #define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */
442 #define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */