Lines Matching +full:0 +full:x2300
17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56 #define MV78XX0_PCIE_MEM_SIZE 0x30000000
58 #define MV78XX0_MBUS_SRAM_TARGET 0x09
59 #define MV78XX0_MBUS_SRAM_ATTR 0x00
68 #define BRIDGE_WINS_SZ (0xA000)
73 #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
74 #define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
75 #define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
76 #define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
77 #define DDR_WINDOW_CPU_SZ (0x20)
79 #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
80 #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
81 #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
82 #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
83 #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
84 #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
85 #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
86 #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
87 #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
88 #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
89 #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
90 #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
91 #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
92 #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
93 #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
95 #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
96 #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
98 #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
99 #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
100 #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
101 #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
103 #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
104 #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
105 #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
107 #define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
109 #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
110 #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
112 #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
113 #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
114 #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
115 #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
117 #define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
119 #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
124 #define MV78X00_Z0_DEV_ID 0x6381
127 #define MV78100_DEV_ID 0x7810
131 #define MV78200_DEV_ID 0x7820