Lines Matching +full:0 +full:x2300
16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
28 #define L3_TARG_STDERRLOG_CINFO_INFO 0x64
29 #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
30 #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
31 #define L3_FLAGMUX_REGERR0 0xc
32 #define L3_FLAGMUX_MASK0 0x8
36 #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
39 /* 0 0 0 */ "Idle",
40 /* 0 0 1 */ "Write",
41 /* 0 1 0 */ "Read",
42 /* 0 1 1 */ "ReadEx",
43 /* 1 0 0 */ "Read Link",
44 /* 1 0 1 */ "Write Non-Posted",
45 /* 1 1 0 */ "Write Conditional",
93 * @l3_base: base addresses of modules (populated runtime if 0)
123 {0x100, "DMM1",},
124 {0x200, "DMM2",},
125 {0x300, "ABE",},
126 {0x400, "L4CFG",},
127 {0x600, "CLK2PWRDISC",},
128 {0x0, "HOSTCLK1",},
129 {0x900, "L4WAKEUP",},
133 .offset = 0x500,
140 {0x500, "CORTEXM3",},
141 {0x300, "DSS",},
142 {0x100, "GPMC",},
143 {0x400, "ISS",},
144 {0x700, "IVAHD",},
145 {0xD00, "AES1",},
146 {0x900, "L4PER0",},
147 {0x200, "OCMRAM",},
148 {0x100, "GPMCsERROR",},
149 {0x600, "SGX",},
150 {0x800, "SL2",},
151 {0x1600, "C2C",},
152 {0x1100, "PWRDISCCLK1",},
153 {0xF00, "SHA1",},
154 {0xE00, "AES2",},
155 {0xC00, "L4PER3",},
156 {0xA00, "L4PER1",},
157 {0xB00, "L4PER2",},
158 {0x0, "HOSTCLK2",},
159 {0x1800, "CAL",},
160 {0x1700, "LLI",},
164 .offset = 0x1000,
171 {0x0100, "DEBUGSS",},
175 .offset = 0x0200,
181 { 0x00, "MPU"},
182 { 0x04, "CS_ADP"},
183 { 0x05, "xxx"},
184 { 0x08, "DSP"},
185 { 0x0C, "IVAHD"},
186 { 0x10, "ISS"},
187 { 0x11, "DucatiM3"},
188 { 0x12, "FaceDetect"},
189 { 0x14, "SDMA_Rd"},
190 { 0x15, "SDMA_Wr"},
191 { 0x16, "xxx"},
192 { 0x17, "xxx"},
193 { 0x18, "SGX"},
194 { 0x1C, "DSS"},
195 { 0x20, "C2C"},
196 { 0x22, "xxx"},
197 { 0x23, "xxx"},
198 { 0x24, "HSI"},
199 { 0x28, "MMC1"},
200 { 0x29, "MMC2"},
201 { 0x2A, "MMC6"},
202 { 0x2C, "UNIPRO1"},
203 { 0x30, "USBHOSTHS"},
204 { 0x31, "USBOTGHS"},
205 { 0x32, "USBHOSTFS"}
220 .mst_addr_mask = 0xFC,
225 {0x0100, "L3INSTR",},
226 {0x0300, "DEBUGSS",},
227 {0x0, "HOSTCLK3",},
231 .offset = 0x0200,
248 .mst_addr_mask = 0x7E0,
253 {0x2a00, "AES1",},
254 {0x0200, "DMM_P1",},
255 {0x0600, "DSP2_SDMA",},
256 {0x0b00, "EVE2",},
257 {0x1300, "DMM_P2",},
258 {0x2c00, "AES2",},
259 {0x0300, "DSP1_SDMA",},
260 {0x0a00, "EVE1",},
261 {0x0c00, "EVE3",},
262 {0x0d00, "EVE4",},
263 {0x2900, "DSS",},
264 {0x0100, "GPMC",},
265 {0x3700, "PCIE1",},
266 {0x1600, "IVA_CONFIG",},
267 {0x1800, "IVA_SL2IF",},
268 {0x0500, "L4_CFG",},
269 {0x1d00, "L4_WKUP",},
270 {0x3800, "PCIE2",},
271 {0x3300, "SHA2_1",},
272 {0x1200, "GPU",},
273 {0x1000, "IPU1",},
274 {0x1100, "IPU2",},
275 {0x2000, "TPCC_EDMA",},
276 {0x2e00, "TPTC1_EDMA",},
277 {0x2b00, "TPTC2_EDMA",},
278 {0x0700, "VCP1",},
279 {0x2500, "L4_PER2_P3",},
280 {0x0e00, "L4_PER3_P3",},
281 {0x2200, "MMU1",},
282 {0x1400, "PRUSS1",},
283 {0x1500, "PRUSS2"},
284 {0x0800, "VCP1",},
288 .offset = 0x803500,
294 {0x0, "HOST CLK1",},
295 {0x800000, "HOST CLK2",},
296 {0xdead, L3_TARGET_NOT_SUPPORTED,},
297 {0x3400, "SHA2_2",},
298 {0x0900, "BB2D",},
299 {0xdead, L3_TARGET_NOT_SUPPORTED,},
300 {0x2100, "L4_PER1_P3",},
301 {0x1c00, "L4_PER1_P1",},
302 {0x1f00, "L4_PER1_P2",},
303 {0x2300, "L4_PER2_P1",},
304 {0x2400, "L4_PER2_P2",},
305 {0x2600, "L4_PER3_P1",},
306 {0x2700, "L4_PER3_P2",},
307 {0x2f00, "MCASP1",},
308 {0x3000, "MCASP2",},
309 {0x3100, "MCASP3",},
310 {0x2800, "MMU2",},
311 {0x0f00, "OCMC_RAM1",},
312 {0x1700, "OCMC_RAM2",},
313 {0x1900, "OCMC_RAM3",},
314 {0x1e00, "OCMC_ROM",},
315 {0x3900, "QSPI",},
319 .offset = 0x803600,
325 {0x0100, "L3_INSTR"},
326 {0x0300, "DEBUGSS_CT_TBR"},
327 {0x0, "HOST CLK3"},
331 .offset = 0x200,
337 { 0x0, "MPU" },
338 { 0x4, "CS_DAP" },
339 { 0x5, "IEEE1500_2_OCP" },
340 { 0x8, "DSP1_MDMA" },
341 { 0x9, "DSP1_CFG" },
342 { 0xA, "DSP1_DMA" },
343 { 0xB, "DSP2_MDMA" },
344 { 0xC, "DSP2_CFG" },
345 { 0xD, "DSP2_DMA" },
346 { 0xE, "IVA" },
347 { 0x10, "EVE1_P1" },
348 { 0x11, "EVE2_P1" },
349 { 0x12, "EVE3_P1" },
350 { 0x13, "EVE4_P1" },
351 { 0x14, "PRUSS1 PRU1" },
352 { 0x15, "PRUSS1 PRU2" },
353 { 0x16, "PRUSS2 PRU1" },
354 { 0x17, "PRUSS2 PRU2" },
355 { 0x18, "IPU1" },
356 { 0x19, "IPU2" },
357 { 0x1A, "SDMA" },
358 { 0x1B, "CDMA" },
359 { 0x1C, "TC1_EDMA" },
360 { 0x1D, "TC2_EDMA" },
361 { 0x20, "DSS" },
362 { 0x21, "MMU1" },
363 { 0x22, "PCIE1" },
364 { 0x23, "MMU2" },
365 { 0x24, "VIP1" },
366 { 0x25, "VIP2" },
367 { 0x26, "VIP3" },
368 { 0x27, "VPE" },
369 { 0x28, "GPU_P1" },
370 { 0x29, "BB2D" },
371 { 0x29, "GPU_P2" },
372 { 0x2B, "GMAC_SW" },
373 { 0x2C, "USB3" },
374 { 0x2D, "USB2_SS" },
375 { 0x2E, "USB2_ULPI_SS1" },
376 { 0x2F, "USB2_ULPI_SS2" },
377 { 0x30, "CSI2_1" },
378 { 0x31, "CSI2_2" },
379 { 0x33, "SATA" },
380 { 0x34, "EVE1_P2" },
381 { 0x35, "EVE2_P2" },
382 { 0x36, "EVE3_P2" },
383 { 0x37, "EVE4_P2" }
399 .mst_addr_mask = 0xFC,
404 {0xf00, "EMIF",},
405 {0x1200, "DES",},
406 {0x400, "OCMCRAM",},
407 {0x700, "TPTC0",},
408 {0x800, "TPTC1",},
409 {0x900, "TPTC2"},
410 {0xb00, "TPCC",},
411 {0xd00, "DEBUGSS",},
412 {0xdead, L3_TARGET_NOT_SUPPORTED,},
413 {0x200, "SHA",},
414 {0xc00, "SGX530",},
415 {0x500, "AES0",},
416 {0xa00, "L4_FAST",},
417 {0x300, "MPUSS_L2_RAM",},
418 {0x100, "ICSS",},
422 .offset = 0x1000,
428 {0x100, "L4_PER_0",},
429 {0x200, "L4_PER_1",},
430 {0x300, "L4_PER_2",},
431 {0x400, "L4_PER_3",},
432 {0x800, "McASP0",},
433 {0x900, "McASP1",},
434 {0xC00, "MMCHS2",},
435 {0x700, "GPMC",},
436 {0xD00, "L4_FW",},
437 {0xdead, L3_TARGET_NOT_SUPPORTED,},
438 {0x500, "ADCTSC",},
439 {0xE00, "L4_WKUP",},
440 {0xA00, "MAG_CARD",},
444 .offset = 0x600,
450 { 0x0, "M1 (128-bit)"},
451 { 0x1, "M2 (64-bit)"},
452 { 0x4, "DAP"},
453 { 0x5, "P1500"},
454 { 0xC, "ICSS0"},
455 { 0xD, "ICSS1"},
456 { 0x14, "Wakeup Processor"},
457 { 0x18, "TPTC0 Read"},
458 { 0x19, "TPTC0 Write"},
459 { 0x1A, "TPTC1 Read"},
460 { 0x1B, "TPTC1 Write"},
461 { 0x1C, "TPTC2 Read"},
462 { 0x1D, "TPTC2 Write"},
463 { 0x20, "SGX530"},
464 { 0x21, "OCP WP Traffic Probe"},
465 { 0x22, "OCP WP DMA Profiling"},
466 { 0x23, "OCP WP Event Trace"},
467 { 0x25, "DSS"},
468 { 0x28, "Crypto DMA RD"},
469 { 0x29, "Crypto DMA WR"},
470 { 0x2C, "VPFE0"},
471 { 0x2D, "VPFE1"},
472 { 0x30, "GEMAC"},
473 { 0x34, "USB0 RD"},
474 { 0x35, "USB0 WR"},
475 { 0x36, "USB1 RD"},
476 { 0x37, "USB1 WR"},
490 .mst_addr_mask = 0x3F,