Lines Matching +full:0 +full:x2300
12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
56 #define MT_XO_CTRL0 0x0100
57 #define MT_XO_CTRL1 0x0104
58 #define MT_XO_CTRL2 0x0108
59 #define MT_XO_CTRL3 0x010c
60 #define MT_XO_CTRL4 0x0110
62 #define MT_XO_CTRL5 0x0114
65 #define MT_XO_CTRL6 0x0118
68 #define MT_XO_CTRL7 0x011c
70 #define MT_WLAN_MTC_CTRL 0x10148
71 #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
84 #define MT_INT_SOURCE_CSR 0x0200
85 #define MT_INT_MASK_CSR 0x0204
88 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
103 #define MT_WPDMA_GLO_CFG 0x0208
104 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
115 #define MT_WPDMA_RST_IDX 0x020c
117 #define MT_WPDMA_DELAY_INT_CFG 0x0210
119 #define MT_WMM_AIFSN 0x0214
120 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
123 #define MT_WMM_CWMIN 0x0218
124 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
127 #define MT_WMM_CWMAX 0x021c
128 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
131 #define MT_WMM_TXOP_BASE 0x0220
134 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
136 #define MT_FCE_DMA_ADDR 0x0230
137 #define MT_FCE_DMA_LEN 0x0234
139 #define MT_USB_DMA_CFG 0x238
140 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
153 #define MT_TSO_CTRL 0x0250
154 #define MT_HEADER_TRANS_CTRL_REG 0x0260
156 #define MT_US_CYC_CFG 0x02a4
157 #define MT_US_CYC_CNT GENMASK(7, 0)
159 #define MT_TX_RING_BASE 0x0300
160 #define MT_RX_RING_BASE 0x03c0
161 #define MT_RING_SIZE 0x10
166 #define MT_PBF_SYS_CTRL 0x0400
167 #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
173 #define MT_PBF_CFG 0x0404
174 #define MT_PBF_CFG_TX0Q_EN BIT(0)
181 #define MT_PBF_TX_MAX_PCNT 0x0408
182 #define MT_PBF_RX_MAX_PCNT 0x040c
184 #define MT_BCN_OFFSET_BASE 0x041c
187 #define MT_RXQ_STA 0x0430
188 #define MT_TXQ_STA 0x0434
190 #define MT_RF_CSR_CFG 0x0500
191 #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
197 #define MT_RF_BYPASS_0 0x0504
198 #define MT_RF_BYPASS_1 0x0508
199 #define MT_RF_SETTING_0 0x050c
201 #define MT_RF_DATA_WRITE 0x0524
203 #define MT_RF_CTRL 0x0528
204 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
209 #define MT_RF_DATA_READ 0x052c
211 #define MT_FCE_PSE_CTRL 0x0800
212 #define MT_FCE_PARAMETERS 0x0804
213 #define MT_FCE_CSO 0x0808
215 #define MT_FCE_L2_STUFF 0x080c
216 #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
226 #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824
228 #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
229 #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
230 #define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
232 #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
234 #define MT_PAUSE_ENABLE_CONTROL1 0x0a38
236 #define MT_FCE_SKIP_FS 0x0a6c
238 #define MT_MAC_CSR0 0x1000
240 #define MT_MAC_SYS_CTRL 0x1004
241 #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
246 #define MT_MAC_ADDR_DW0 0x1008
247 #define MT_MAC_ADDR_DW1 0x100c
250 #define MT_MAC_BSSID_DW0 0x1010
251 #define MT_MAC_BSSID_DW1 0x1014
252 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
260 #define MT_MAX_LEN_CFG 0x1018
263 #define MT_BBP_CSR_CFG 0x101c
264 #define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)
271 #define MT_AMPDU_MAX_LEN_20M1S 0x1030
272 #define MT_AMPDU_MAX_LEN_20M2S 0x1034
273 #define MT_AMPDU_MAX_LEN_40M1S 0x1038
274 #define MT_AMPDU_MAX_LEN_40M2S 0x103c
275 #define MT_AMPDU_MAX_LEN 0x1040
277 #define MT_WCID_DROP_BASE 0x106c
281 #define MT_BCN_BYPASS_MASK 0x108c
283 #define MT_MAC_APC_BSSID_BASE 0x1090
286 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
289 #define MT_XIFS_TIME_CFG 0x1100
290 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
296 #define MT_BKOFF_SLOT_CFG 0x1104
297 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
300 #define MT_BEACON_TIME_CFG 0x1114
301 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
308 #define MT_TBTT_SYNC_CFG 0x1118
309 #define MT_TBTT_TIMER_CFG 0x1124
311 #define MT_INT_TIMER_CFG 0x1128
312 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
315 #define MT_INT_TIMER_EN 0x112c
316 #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
319 #define MT_MAC_STATUS 0x1200
320 #define MT_MAC_STATUS_TX BIT(0)
323 #define MT_PWR_PIN_CFG 0x1204
324 #define MT_AUX_CLK_CFG 0x120c
326 #define MT_BB_PA_MODE_CFG0 0x1214
327 #define MT_BB_PA_MODE_CFG1 0x1218
328 #define MT_RF_PA_MODE_CFG0 0x121c
329 #define MT_RF_PA_MODE_CFG1 0x1220
331 #define MT_RF_PA_MODE_ADJ0 0x1228
332 #define MT_RF_PA_MODE_ADJ1 0x122c
334 #define MT_DACCLK_EN_DLY_CFG 0x1264
336 #define MT_EDCA_CFG_BASE 0x1300
338 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
343 #define MT_TX_PWR_CFG_0 0x1314
344 #define MT_TX_PWR_CFG_1 0x1318
345 #define MT_TX_PWR_CFG_2 0x131c
346 #define MT_TX_PWR_CFG_3 0x1320
347 #define MT_TX_PWR_CFG_4 0x1324
349 #define MT_TX_BAND_CFG 0x132c
350 #define MT_TX_BAND_CFG_UPPER_40M BIT(0)
354 #define MT_HT_FBK_TO_LEGACY 0x1384
355 #define MT_TX_MPDU_ADJ_INT 0x1388
357 #define MT_TX_PWR_CFG_7 0x13d4
358 #define MT_TX_PWR_CFG_8 0x13d8
359 #define MT_TX_PWR_CFG_9 0x13dc
361 #define MT_TX_SW_CFG0 0x1330
362 #define MT_TX_SW_CFG1 0x1334
363 #define MT_TX_SW_CFG2 0x1338
365 #define MT_TXOP_CTRL_CFG 0x1340
366 #define MT_TXOP_TRUN_EN GENMASK(5, 0)
370 #define MT_TX_RTS_CFG 0x1344
371 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
375 #define MT_TX_TIMEOUT_CFG 0x1348
376 #define MT_TX_RETRY_CFG 0x134c
377 #define MT_TX_LINK_CFG 0x1350
378 #define MT_HT_FBK_CFG0 0x1354
379 #define MT_HT_FBK_CFG1 0x1358
380 #define MT_LG_FBK_CFG0 0x135c
381 #define MT_LG_FBK_CFG1 0x1360
383 #define MT_CCK_PROT_CFG 0x1364
384 #define MT_OFDM_PROT_CFG 0x1368
385 #define MT_MM20_PROT_CFG 0x136c
386 #define MT_MM40_PROT_CFG 0x1370
387 #define MT_GF20_PROT_CFG 0x1374
388 #define MT_GF40_PROT_CFG 0x1378
390 #define MT_PROT_RATE GENMASK(15, 0)
402 #define MT_PROT_RATE_CCK_11 0x0003
403 #define MT_PROT_RATE_OFDM_6 0x4000
404 #define MT_PROT_RATE_OFDM_24 0x4004
405 #define MT_PROT_RATE_DUP_OFDM_24 0x4084
411 #define MT_EXP_ACK_TIME 0x1380
413 #define MT_TX_PWR_CFG_0_EXT 0x1390
414 #define MT_TX_PWR_CFG_1_EXT 0x1394
416 #define MT_TX_FBK_LIMIT 0x1398
417 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
423 #define MT_TX0_RF_GAIN_CORR 0x13a0
424 #define MT_TX1_RF_GAIN_CORR 0x13a4
425 #define MT_TX0_RF_GAIN_ATTEN 0x13a8
427 #define MT_TX_ALC_CFG_0 0x13b0
428 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
433 #define MT_TX_ALC_CFG_1 0x13b4
434 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
436 #define MT_TX_ALC_CFG_2 0x13a8
437 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
439 #define MT_TX0_BB_GAIN_ATTEN 0x13c0
441 #define MT_TX_ALC_VGA3 0x13c8
443 #define MT_TX_PROT_CFG6 0x13e0
444 #define MT_TX_PROT_CFG7 0x13e4
445 #define MT_TX_PROT_CFG8 0x13e8
447 #define MT_PIFS_TX_CFG 0x13ec
449 #define MT_RX_FILTR_CFG 0x1400
451 #define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
469 #define MT_AUTO_RSP_CFG 0x1404
473 #define MT_LEGACY_BASIC_RATE 0x1408
474 #define MT_HT_BASIC_RATE 0x140c
476 #define MT_RX_PARSER_CFG 0x1418
477 #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
479 #define MT_EXT_CCA_CFG 0x141c
480 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
487 #define MT_TX_SW_CFG3 0x1478
489 #define MT_PN_PAD_MODE 0x150c
491 #define MT_TXOP_HLDR_ET 0x1608
493 #define MT_PROT_AUTO_TX_CFG 0x1648
495 #define MT_RX_STA_CNT0 0x1700
496 #define MT_RX_STA_CNT1 0x1704
497 #define MT_RX_STA_CNT2 0x1708
498 #define MT_TX_STA_CNT0 0x170c
499 #define MT_TX_STA_CNT1 0x1710
500 #define MT_TX_STA_CNT2 0x1714
510 #define MT_TX_STAT_FIFO 0x1718
511 #define MT_TX_STAT_FIFO_VALID BIT(0)
519 #define MT_TX_AGG_STAT 0x171c
521 #define MT_TX_AGG_CNT_BASE0 0x1720
523 #define MT_MPDU_DENSITY_CNT 0x1740
525 #define MT_TX_AGG_CNT_BASE1 0x174c
531 #define MT_TX_STAT_FIFO_EXT 0x1798
532 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
534 #define MT_BBP_CORE_BASE 0x2000
535 #define MT_BBP_IBI_BASE 0x2100
536 #define MT_BBP_AGC_BASE 0x2300
537 #define MT_BBP_TXC_BASE 0x2400
538 #define MT_BBP_RXC_BASE 0x2500
539 #define MT_BBP_TXO_BASE 0x2600
540 #define MT_BBP_TXBE_BASE 0x2700
541 #define MT_BBP_RXFE_BASE 0x2800
542 #define MT_BBP_RXO_BASE 0x2900
543 #define MT_BBP_DFS_BASE 0x2a00
544 #define MT_BBP_TR_BASE 0x2b00
545 #define MT_BBP_CAL_BASE 0x2c00
546 #define MT_BBP_DSC_BASE 0x2e00
547 #define MT_BBP_PFMU_BASE 0x2f00
562 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
565 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
567 #define MT_WCID_ADDR_BASE 0x1800
570 #define MT_SRAM_BASE 0x4000
572 #define MT_WCID_KEY_BASE 0x8000
575 #define MT_WCID_IV_BASE 0xa000
578 #define MT_WCID_ATTR_BASE 0xa800
581 #define MT_WCID_ATTR_PAIRWISE BIT(0)
590 #define MT_SKEY_BASE_0 0xac00
591 #define MT_SKEY_BASE_1 0xb400
599 #define MT_SKEY_MODE_BASE_0 0xb000
600 #define MT_SKEY_MODE_BASE_1 0xb3f0
607 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
610 #define MT_BEACON_BASE 0xc000
612 #define MT_TEMP_SENSOR 0x1d000
613 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)