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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-mx8menlo.dts22 pinctrl-0 = <&pinctrl_led>;
40 pinctrl-0 = <&pinctrl_beeper>;
47 #clock-cells = <0>;
54 #size-cells = <0>;
56 pinctrl-0 = <&pinctrl_ecspi1>;
61 canfd: can@0 {
66 reg = <0>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
77 spidev@0 {
79 reg = <0>;
[all …]
H A Dimx8mp-verdin.dtsi25 brightness-levels = <0 45 63 88 119 158 203 255>;
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 45 63 88 119 158 203 255>;
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
53 pinctrl-0 = <&pinctrl_usb_1_id>;
68 pinctrl-0 = <&pinctrl_gpio_keys>;
73 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
109 pinctrl-0 = <&pinctrl_reg_eth>;
125 pinctrl-0
[all...]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dmediatek,efuse.yaml23 pattern: "^efuse@[0-9a-f]+$"
56 reg = <0x11c10000 0x1000>;
61 reg = <0x184 0x1>;
62 bits = <0 5>;
65 reg = <0x184 0x
[all...]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x
[all...]
H A Dbrcm,spi-bcm-qspi.txt22 Must be <0>, also as required by generic SPI binding.
89 #address-cells = <0x1>;
90 #size-cells = <0x0>;
92 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
94 interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
95 interrupt-parent = <0x1c>;
107 m25p80@0 {
108 #size-cells = <0x2>;
109 #address-cells = <0x2>;
111 reg = <0x0>;
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
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/freebsd/contrib/netbsd-tests/lib/libcurses/tests/
H A Dstd_defines8 assign TRUE 0x01
9 assign FALSE 0x00
13 assign COLOR_BLACK 0x00
14 assign COLOR_RED 0x01
15 assign COLOR_GREEN 0x02
16 assign COLOR_YELLOW 0x03
17 assign COLOR_BLUE 0x04
18 assign COLOR_MAGENTA 0x05
19 assign COLOR_CYAN 0x06
20 assign COLOR_WHITE 0x07
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Despressif9 # cfg_holder=4617=0x1209
10 0 uleshort 4617
11 # remaining settings normally 0x5A+offset XORed; free_1D5[20] empty since 5.12.0e
12 >0x1D5 ubequad 0x2f30313233343536 configuration of Tasmota firmware (ESP8266)
15 # version like 6.2.1.0 ~ 0x06020100 XORed to 0x63666262
16 >>11 ubyte^0x65 x \b, version %u
17 >>10 ubyte^0x64 x \b.%u
18 >>9 ubyte^0x63 x \b.%u
19 >>8 ubyte^0x62 x \b.%u
22 >>0x165 ubyte^0x1BF x \b, hostname %c
[all …]
/freebsd/sys/dev/ioat/
H A Dioat_hw.h31 #define IOAT_CHANCNT_OFFSET 0x00
33 #define IOAT_XFERCAP_OFFSET 0x01
34 /* Only bits [4:0] are valid. */
35 #define IOAT_XFERCAP_VALID_MASK 0x1f
37 #define IOAT_GENCTRL_OFFSET 0x02
39 #define IOAT_INTRCTRL_OFFSET 0x03
40 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01
42 #define IOAT_ATTNSTATUS_OFFSET 0x04
44 #define IOAT_CBVER_OFFSET 0x08
46 #define IOAT_INTRDELAY_OFFSET 0x0C
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_gen4vf_hw_csr_data.h6 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0
7 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
8 #define ADF_RING_CSR_RING_HEAD 0x0C0
9 #define ADF_RING_CSR_RING_TAIL 0x100
10 #define ADF_RING_CSR_E_STAT 0x14C
11 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000
12 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040
13 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080
14 #define ADF_RING_CSR_INT_FLAG 0x170
15 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm5301x.dtsi13 a9pll: arm_clk@0 {
14 #clock-cells = <0>;
17 reg = <0x00000 0x1000>;
22 reg = <0x20620 0x20>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
[all...]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhi3620-hi4511.dts22 reg = <0x40000000 0x20000000>;
32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
39 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
46 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
53 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
60 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
67 pinctrl-0 = <&board_pmx_pins>;
71 0x008 0x0 /* GPIO -- eFUSE_DOUT */
72 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
77 0x0f0 0x0
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
25 { "PIDX", 0, 13 },
26 { "SGE_VF_GTS", 0x004, 0 },
30 { "CIDXInc", 0, 12 },
32 { NULL, 0, 0 }
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatopreg.h32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000
33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004
34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008
35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C
36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F
39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16)
40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010
41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dadf_transport_access_macros.h7 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
8 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
9 #define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF
10 #define ADF_RING_CSR_RING_CONFIG 0x000
11 #define ADF_RING_CSR_RING_LBASE 0x040
12 #define ADF_RING_CSR_RING_UBASE 0x080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
[all …]
H A Dadf_gen4_hw_data.h9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10 #define ADF_RING_CSR_RING_CONFIG 0x1000
11 #define ADF_RING_CSR_RING_LBASE 0x1040
12 #define ADF_RING_CSR_RING_UBASE 0x1080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_COL_CTL 0x180
[all …]
H A Dadf_gen2_hw_data.h10 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12 #define ADF_RING_CSR_RING_CONFIG 0x000
13 #define ADF_RING_CSR_RING_LBASE 0x040
14 #define ADF_RING_CSR_RING_UBASE 0x080
15 #define ADF_RING_CSR_RING_HEAD 0x0C0
16 #define ADF_RING_CSR_RING_TAIL 0x100
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_INT_FLAG 0x170
19 #define ADF_RING_CSR_INT_SRCSEL 0x174
[all …]

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