1*54912308SNavdeep Parhar /* 2*54912308SNavdeep Parhar * This file is _NOT_ automatically generated. It must agree with the 3*54912308SNavdeep Parhar * Virtual Function register map definitions in t4vf_defs.h in the common 4*54912308SNavdeep Parhar * code. 5*54912308SNavdeep Parhar */ 6*54912308SNavdeep Parhar struct reg_info t4vf_sge_regs[] = { 7*54912308SNavdeep Parhar { "SGE_KDOORBELL", 0x000, 0 }, 8*54912308SNavdeep Parhar { "QID", 15, 17 }, 9*54912308SNavdeep Parhar { "Priority", 14, 1 }, 10*54912308SNavdeep Parhar { "PIDX", 0, 14 }, 11*54912308SNavdeep Parhar { "SGE_GTS", 0x004, 0 }, 12*54912308SNavdeep Parhar { "IngressQID", 16, 16 }, 13*54912308SNavdeep Parhar { "TimerReg", 13, 3 }, 14*54912308SNavdeep Parhar { "SEIntArm", 12, 1 }, 15*54912308SNavdeep Parhar { "CIDXInc", 0, 12 }, 16*54912308SNavdeep Parhar 17*54912308SNavdeep Parhar { NULL, 0, 0 } 18*54912308SNavdeep Parhar }; 19*54912308SNavdeep Parhar 20*54912308SNavdeep Parhar struct reg_info t5vf_sge_regs[] = { 21*54912308SNavdeep Parhar { "SGE_VF_KDOORBELL", 0x000, 0 }, 22*54912308SNavdeep Parhar { "QID", 15, 17 }, 23*54912308SNavdeep Parhar { "Priority", 14, 1 }, 24*54912308SNavdeep Parhar { "Type", 13, 1 }, 25*54912308SNavdeep Parhar { "PIDX", 0, 13 }, 26*54912308SNavdeep Parhar { "SGE_VF_GTS", 0x004, 0 }, 27*54912308SNavdeep Parhar { "IngressQID", 16, 16 }, 28*54912308SNavdeep Parhar { "TimerReg", 13, 3 }, 29*54912308SNavdeep Parhar { "SEIntArm", 12, 1 }, 30*54912308SNavdeep Parhar { "CIDXInc", 0, 12 }, 31*54912308SNavdeep Parhar 32*54912308SNavdeep Parhar { NULL, 0, 0 } 33*54912308SNavdeep Parhar }; 34*54912308SNavdeep Parhar 35*54912308SNavdeep Parhar struct reg_info t4vf_mps_regs[] = { 36*54912308SNavdeep Parhar { "MPS_VF_CTL", 0x100, 0 }, 37*54912308SNavdeep Parhar { "TxEn", 1, 1 }, 38*54912308SNavdeep Parhar { "RxEn", 0, 1 }, 39*54912308SNavdeep Parhar 40*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_BCAST_BYTES_L", 0x180, 0 }, 41*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_BCAST_BYTES_H", 0x184, 0 }, 42*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_BCAST_FRAMES_L", 0x188, 0 }, 43*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_BCAST_FRAMES_H", 0x18c, 0 }, 44*54912308SNavdeep Parhar 45*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_MCAST_BYTES_L", 0x190, 0 }, 46*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_MCAST_BYTES_H", 0x194, 0 }, 47*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_MCAST_FRAMES_L", 0x198, 0 }, 48*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_MCAST_FRAMES_H", 0x19c, 0 }, 49*54912308SNavdeep Parhar 50*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_UCAST_BYTES_L", 0x1a0, 0 }, 51*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_UCAST_BYTES_H", 0x1a4, 0 }, 52*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_UCAST_FRAMES_L", 0x1a8, 0 }, 53*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_UCAST_FRAMES_H", 0x1ac, 0 }, 54*54912308SNavdeep Parhar 55*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_DROP_FRAMES_L", 0x1b0, 0 }, 56*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_DROP_FRAMES_H", 0x1b4, 0 }, 57*54912308SNavdeep Parhar 58*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L", 0x1b8, 0 }, 59*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H", 0x1bc, 0 }, 60*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L", 0x1c0, 0 }, 61*54912308SNavdeep Parhar { "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H", 0x1c4, 0 }, 62*54912308SNavdeep Parhar 63*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_BCAST_BYTES_L", 0x1c8, 0 }, 64*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_BCAST_BYTES_H", 0x1cc, 0 }, 65*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_BCAST_FRAMES_L", 0x1d0, 0 }, 66*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_BCAST_FRAMES_H", 0x1d4, 0 }, 67*54912308SNavdeep Parhar 68*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_MCAST_BYTES_L", 0x1d8, 0 }, 69*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_MCAST_BYTES_H", 0x1dc, 0 }, 70*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_MCAST_FRAMES_L", 0x1e0, 0 }, 71*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_MCAST_FRAMES_H", 0x1e4, 0 }, 72*54912308SNavdeep Parhar 73*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_UCAST_BYTES_L", 0x1e8, 0 }, 74*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_UCAST_BYTES_H", 0x1ec, 0 }, 75*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_UCAST_FRAMES_L", 0x1f0, 0 }, 76*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_UCAST_FRAMES_H", 0x1f4, 0 }, 77*54912308SNavdeep Parhar 78*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_ERR_FRAMES_L", 0x1f8, 0 }, 79*54912308SNavdeep Parhar { "MPS_VF_STAT_RX_VF_ERR_FRAMES_H", 0x1fc, 0 }, 80*54912308SNavdeep Parhar 81*54912308SNavdeep Parhar { NULL, 0, 0 } 82*54912308SNavdeep Parhar }; 83*54912308SNavdeep Parhar 84*54912308SNavdeep Parhar struct reg_info t4vf_pl_regs[] = { 85*54912308SNavdeep Parhar { "PL_VF_WHOAMI", 0x200, 0 }, 86*54912308SNavdeep Parhar { "PortxMap", 24, 3 }, 87*54912308SNavdeep Parhar { "SourceBus", 16, 2 }, 88*54912308SNavdeep Parhar { "SourcePF", 8, 3 }, 89*54912308SNavdeep Parhar { "IsVF", 7, 1 }, 90*54912308SNavdeep Parhar { "VFID", 0, 7 }, 91*54912308SNavdeep Parhar 92*54912308SNavdeep Parhar { NULL, 0, 0 } 93*54912308SNavdeep Parhar }; 94*54912308SNavdeep Parhar 95*54912308SNavdeep Parhar struct reg_info t5vf_pl_regs[] = { 96*54912308SNavdeep Parhar { "PL_WHOAMI", 0x200, 0 }, 97*54912308SNavdeep Parhar { "PortxMap", 24, 3 }, 98*54912308SNavdeep Parhar { "SourceBus", 16, 2 }, 99*54912308SNavdeep Parhar { "SourcePF", 8, 3 }, 100*54912308SNavdeep Parhar { "IsVF", 7, 1 }, 101*54912308SNavdeep Parhar { "VFID", 0, 7 }, 102*54912308SNavdeep Parhar { "PL_VF_REV", 0x204, 0 }, 103*54912308SNavdeep Parhar { "ChipID", 4, 4 }, 104*54912308SNavdeep Parhar { "Rev", 0, 4 }, 105*54912308SNavdeep Parhar { "PL_VF_REVISION", 0x208, 0 }, 106*54912308SNavdeep Parhar 107*54912308SNavdeep Parhar { NULL, 0, 0 } 108*54912308SNavdeep Parhar }; 109*54912308SNavdeep Parhar 110*54912308SNavdeep Parhar struct reg_info t6vf_pl_regs[] = { 111*54912308SNavdeep Parhar { "PL_WHOAMI", 0x200, 0 }, 112*54912308SNavdeep Parhar { "PortxMap", 24, 3 }, 113*54912308SNavdeep Parhar { "SourceBus", 16, 2 }, 114*54912308SNavdeep Parhar { "SourcePF", 9, 3 }, 115*54912308SNavdeep Parhar { "IsVF", 8, 1 }, 116*54912308SNavdeep Parhar { "VFID", 0, 8 }, 117*54912308SNavdeep Parhar { "PL_VF_REV", 0x204, 0 }, 118*54912308SNavdeep Parhar { "ChipID", 4, 4 }, 119*54912308SNavdeep Parhar { "Rev", 0, 4 }, 120*54912308SNavdeep Parhar { "PL_VF_REVISION", 0x208, 0 }, 121*54912308SNavdeep Parhar 122*54912308SNavdeep Parhar { NULL, 0, 0 } 123*54912308SNavdeep Parhar }; 124*54912308SNavdeep Parhar 125*54912308SNavdeep Parhar struct reg_info t4vf_cim_regs[] = { 126*54912308SNavdeep Parhar /* 127*54912308SNavdeep Parhar * Note: the Mailbox Control register has read side-effects so 128*54912308SNavdeep Parhar * the driver simply returns 0xffff for this register. 129*54912308SNavdeep Parhar */ 130*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_CTRL", 0x300, 0 }, 131*54912308SNavdeep Parhar { "MBGeneric", 4, 4 }, 132*54912308SNavdeep Parhar { "MBMsgValid", 3, 1 }, 133*54912308SNavdeep Parhar { "MBIntReq", 2, 1 }, 134*54912308SNavdeep Parhar { "MBOwner", 0, 2 }, 135*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_STATUS", 0x304, 0 }, 136*54912308SNavdeep Parhar { "MBVFReady", 0, 1 }, 137*54912308SNavdeep Parhar 138*54912308SNavdeep Parhar { NULL, 0, 0 } 139*54912308SNavdeep Parhar }; 140*54912308SNavdeep Parhar 141*54912308SNavdeep Parhar struct reg_info t4vf_mbdata_regs[] = { 142*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_00", 0x240, 0 }, 143*54912308SNavdeep Parhar { "Return", 8, 8 }, 144*54912308SNavdeep Parhar { "Length16", 0, 8 }, 145*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_04", 0x244, 0 }, 146*54912308SNavdeep Parhar { "OpCode", 24, 8 }, 147*54912308SNavdeep Parhar { "Request", 23, 1 }, 148*54912308SNavdeep Parhar { "Read", 22, 1 }, 149*54912308SNavdeep Parhar { "Write", 21, 1 }, 150*54912308SNavdeep Parhar { "Execute", 20, 1 }, 151*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_08", 0x248, 0 }, 152*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_0c", 0x24c, 0 }, 153*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_10", 0x250, 0 }, 154*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_14", 0x254, 0 }, 155*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_18", 0x258, 0 }, 156*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_1c", 0x25c, 0 }, 157*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_20", 0x260, 0 }, 158*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_24", 0x264, 0 }, 159*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_28", 0x268, 0 }, 160*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_2c", 0x26c, 0 }, 161*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_30", 0x270, 0 }, 162*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_34", 0x274, 0 }, 163*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_38", 0x278, 0 }, 164*54912308SNavdeep Parhar { "CIM_VF_EXT_MAILBOX_DATA_3c", 0x27c, 0 }, 165*54912308SNavdeep Parhar 166*54912308SNavdeep Parhar { NULL, 0, 0 } 167*54912308SNavdeep Parhar }; 168