sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

ioat(4): Export HW capabilities to consumers

Merge ^/head r295601 through r295844.

MFH

Sponsored by: The FreeBSD Foundation

ioat(4): Decode/define more capabilities, operations

These are defined in the Intel Haswell EDS volume 2 (registers) (507849
v2.1).

Sponsored by: EMC / Isilon Storage Division

MFH r289384-r293170

Sponsored by: The FreeBSD Foundation

MFH @r292599

This includes the pluggable TCP framework and other chnages to the
netstack to track for VNET stability.

Security: The FreeBSD Foundation

ioat(4): Add an API to get HW revision

Different revisions support different operations. Refer to Intel
External Design Specifications to figure out what your hardware
supports.

Sponsored by: EMC

ioat(4): Add an API to get HW revision

Different revisions support different operations. Refer to Intel
External Design Specifications to figure out what your hardware
supports.

Sponsored by: EMC / Isilon Storage Division

show more ...

ioat(4): Add support for interrupt coalescing

In I/OAT, this is done through the INTRDELAY register. On supported
platforms, this register can coalesce interrupts in a set period to
avoid excessive

ioat(4): Add support for interrupt coalescing

In I/OAT, this is done through the INTRDELAY register. On supported
platforms, this register can coalesce interrupts in a set period to
avoid excessive interrupt load for small descriptor workflows. The
period is configurable anywhere from 1 microsecond to 16.38
milliseconds, in microsecond granularity.

Sponsored by: EMC / Isilon Storage Division

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Catch up with head (r291075).

Merge from head

ioat: Handle channel-fatal HW errors safely

Certain invalid operations trigger hardware error conditions. Error
conditions that only halt one channel can be detected and recovered by
resetting the

ioat: Handle channel-fatal HW errors safely

Certain invalid operations trigger hardware error conditions. Error
conditions that only halt one channel can be detected and recovered by
resetting the channel. Error conditions that halt the whole device are
generally not recoverable.

Add a sysctl to inject channel-fatal HW errors,
'dev.ioat.<N>.force_hw_error=1'.

When a halt due to a channel error is detected, ioat(4) blocks new
operations from being queued on the channel, completes any outstanding
operations with an error status, and resets the channel before allowing
new operations to be queued again.

Update ioat.4 to document error recovery; document blockfill introduced
in r290021 while we are here; document ioat_put_dmaengine() added in
r289907; document DMA_NO_WAIT added in r289982.

Sponsored by: EMC / Isilon Storage Division

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Merge from head

Sponsored by: Gandi.net

ioat: Define DMACAPABILITY bits

Check for BFILL capability before initiating blockfill operations.

Sponsored by: EMC / Isilon Storage Division

ioat: Add %b format string for CHANERR codes

Sponsored by: EMC / Isilon Storage Division

ioat: Actually bring the hardware back online after reset

We need to reset the chancmp and chainaddr MMIO registers to bring the
device back to a working state.

Name the chanerr bits while we're he

ioat: Actually bring the hardware back online after reset

We need to reset the chancmp and chainaddr MMIO registers to bring the
device back to a working state.

Name the chanerr bits while we're here.

Sponsored by: EMC / Isilon Storage Division

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ioat: Define IOAT_XFERCAP_VALID_MASK and use in ioat_read_xfercap

Instead of ANDing a magic constant later.

Sponsored by: EMC / Isilon Storage Division

Finish merging from head, messed up in previous attempt

Merge r286744-r287584 from head.

Merge ^/head r286858 through r287489.

Merge from HEAD

Import ioat(4) driver

I/OAT is also referred to as Crystal Beach DMA and is a Platform Storage
Extension (PSE) on some Intel server platforms.

This driver currently supports DMA descriptors only an

Import ioat(4) driver

I/OAT is also referred to as Crystal Beach DMA and is a Platform Storage
Extension (PSE) on some Intel server platforms.

This driver currently supports DMA descriptors only and is part of a
larger effort to upstream an interconnect between multiple systems using
the Non-Transparent Bridge (NTB) PSE.

For now, this driver is only built on AMD64 platforms. It may be ported
to work on i386 later, if that is desired. The hardware is exclusive to
x86.

Further documentation on ioat(4), including API documentation and usage,
can be found in the new manual page.

Bring in a test tool, ioatcontrol(8), in tools/tools/ioat. The test
tool is not hooked up to the build and is not intended for end users.

Submitted by: jimharris, Carl Delsey <carl.r.delsey@intel.com>
Reviewed by: jimharris (reviewed my changes)
Approved by: markj (mentor)
Relnotes: yes
Sponsored by: Intel
Sponsored by: EMC / Isilon Storage Division
Differential Revision: https://reviews.freebsd.org/D3456

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