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/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-edp-legacy.yaml63 # LG 12.9" (2560x1700 pixels) TFT LCD panel
104 hsync-active = <0>;
109 vsync-active = <0>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dpm6150.dtsi22 hysteresis = <0>;
28 hysteresis = <0>;
37 pm6150_lsid0: pmic@0 {
39 reg = <0x0 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x800>;
46 mode-bootloader = <0x2>;
47 mode-recovery = <0x1>;
51 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
59 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm8150b.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
44 reg = <0x2 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
58 reg = <0x1100>;
64 reg = <0x1500>,
65 <0x1700>;
66 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
[all …]
H A Dpm7250b.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>,
56 <0x1700>;
57 interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
58 <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
59 <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
H A Dapq8096-db820c.dtsi62 #clock-cells = <0>;
67 pinctrl-0 = <&divclk4_pin_a>;
72 pinctrl-0 = <&audio_mclk>;
75 #clock-cells = <0>;
76 enable-gpios = <&pm8994_gpios 15 0>;
83 #size-cells = <0>;
87 pinctrl-0 = <&volume_up_gpio>;
89 button@0 {
100 pinctrl-0 = <&usb2_vbus_det_gpio>;
107 pinctrl-0 = <&usb3_vbus_det_gpio>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc2.yaml25 - const: ingenic,x1700-otg
197 reg = <0x10180000 0x40000>;
H A Dqcom,pmic-typec.yaml136 #size-cells = <0>;
140 reg = <0x1500>,
141 <0x1700>;
143 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
144 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
145 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
146 <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
147 <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
148 <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
149 <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
[all...]
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
[all...]
/freebsd/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dreg.h8 #define REG_SYS_FUNC_EN 0x0002
13 #define BIT_FEN_BB_RSTB BIT(0)
16 #define REG_SYS_PW_CTRL 0x0004
18 #define REG_SYS_CLK_CTRL 0x0008
21 #define REG_SYS_CLKR 0x0008
26 #define REG_RSV_CTRL 0x001C
27 #define DISABLE_PI 0x3
28 #define ENABLE_PI 0x2
30 #define BIT_WLMCU_IOIF BIT(0)
31 #define REG_RF_CTRL 0x001
[all...]
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
/freebsd/sys/dev/drm2/
H A Ddrm_pciids.h14 {0, 0, 0, NULL}
17 {0x3D3D, 0x0008, 0, "3DLabs GLINT Gamma G1"}, \
18 {0, 0, 0, NULL}
21 {0x8086, 0x1132, 0, "Intel i815 GMCH"}, \
22 {0x8086, 0x7121, 0, "Intel i810 GMCH"}, \
23 {0x8086, 0x7123, 0, "Intel i810-DC100 GMCH"}, \
24 {0x8086, 0x7125, 0, "Intel i810E GMCH"}, \
25 {0, 0, 0, NULL}
28 {0x8086, 0x2562, 0, "Intel i845G GMCH"}, \
29 {0x8086, 0x2572, 0, "Intel i865G GMCH"}, \
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
H A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
40 clock-frequency = <0>;
44 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
54 clock-frequency = <0>;
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_mtwreg.h19 #define MTW_ASIC_VER 0x0000
20 #define MTW_CMB_CTRL 0x0020
21 #define MTW_EFUSE_CTRL 0x0024
22 #define MTW_EFUSE_DATA0 0x0028
23 #define MTW_EFUSE_DATA1 0x002c
24 #define MTW_EFUSE_DATA2 0x0030
25 #define MTW_EFUSE_DATA3 0x0034
26 #define MTW_OSC_CTRL 0x0038
27 #define MTW_COEX_CFG0 0x0040
28 #define MTW_PLL_CTRL 0x0050
[all …]

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