1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * STx/Freescale ADS5125 MPC5125 silicon 4 * 5 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. 6 * 7 * Reworked by Matteo Facchinetti (engineering@sirius-es.it) 8 * Copyright (C) 2013 Sirius Electronic Systems 9 */ 10 11#include <dt-bindings/clock/mpc512x-clock.h> 12 13/dts-v1/; 14 15/ { 16 model = "mpc5125twr"; // In BSP "mpc5125ads" 17 compatible = "fsl,mpc5125ads", "fsl,mpc5125"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 interrupt-parent = <&ipic>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 ethernet0 = ð0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,5125@0 { 33 device_type = "cpu"; 34 reg = <0>; 35 d-cache-line-size = <0x20>; // 32 bytes 36 i-cache-line-size = <0x20>; // 32 bytes 37 d-cache-size = <0x8000>; // L1, 32K 38 i-cache-size = <0x8000>; // L1, 32K 39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4) 40 bus-frequency = <198000000>; // 198 MHz csb bus 41 clock-frequency = <396000000>; // 396 MHz ppc core 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x10000000>; // 256MB at 0 48 }; 49 50 sram@30000000 { 51 compatible = "fsl,mpc5121-sram"; 52 reg = <0x30000000 0x08000>; // 32K at 0x30000000 53 }; 54 55 clocks { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 osc: osc { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <33000000>; 63 }; 64 }; 65 66 soc@80000000 { 67 compatible = "fsl,mpc5121-immr"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges = <0x0 0x80000000 0x400000>; 71 reg = <0x80000000 0x400000>; 72 bus-frequency = <66000000>; // 66 MHz ips bus 73 74 // IPIC 75 // interrupts cell = <intr #, sense> 76 // sense values match linux IORESOURCE_IRQ_* defines: 77 // sense == 8: Level, low assertion 78 // sense == 2: Edge, high-to-low change 79 // 80 ipic: interrupt-controller@c00 { 81 compatible = "fsl,mpc5121-ipic", "fsl,ipic"; 82 interrupt-controller; 83 #address-cells = <0>; 84 #interrupt-cells = <2>; 85 reg = <0xc00 0x100>; 86 }; 87 88 rtc@a00 { // Real time clock 89 compatible = "fsl,mpc5121-rtc"; 90 reg = <0xa00 0x100>; 91 interrupts = <79 0x8 80 0x8>; 92 }; 93 94 reset@e00 { // Reset module 95 compatible = "fsl,mpc5125-reset"; 96 reg = <0xe00 0x100>; 97 }; 98 99 clks: clock@f00 { // Clock control 100 compatible = "fsl,mpc5121-clock"; 101 reg = <0xf00 0x100>; 102 #clock-cells = <1>; 103 clocks = <&osc>; 104 clock-names = "osc"; 105 }; 106 107 pmc@1000 { // Power Management Controller 108 compatible = "fsl,mpc5121-pmc"; 109 reg = <0x1000 0x100>; 110 interrupts = <83 0x2>; 111 }; 112 113 gpio0: gpio@1100 { 114 compatible = "fsl,mpc5125-gpio"; 115 reg = <0x1100 0x080>; 116 interrupts = <78 0x8>; 117 }; 118 119 gpio1: gpio@1180 { 120 compatible = "fsl,mpc5125-gpio"; 121 reg = <0x1180 0x080>; 122 interrupts = <86 0x8>; 123 }; 124 125 can@1300 { // CAN rev.2 126 compatible = "fsl,mpc5121-mscan"; 127 interrupts = <12 0x8>; 128 reg = <0x1300 0x80>; 129 clocks = <&clks MPC512x_CLK_BDLC>, 130 <&clks MPC512x_CLK_IPS>, 131 <&clks MPC512x_CLK_SYS>, 132 <&clks MPC512x_CLK_REF>, 133 <&clks MPC512x_CLK_MSCAN0_MCLK>; 134 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 135 }; 136 137 can@1380 { 138 compatible = "fsl,mpc5121-mscan"; 139 interrupts = <13 0x8>; 140 reg = <0x1380 0x80>; 141 clocks = <&clks MPC512x_CLK_BDLC>, 142 <&clks MPC512x_CLK_IPS>, 143 <&clks MPC512x_CLK_SYS>, 144 <&clks MPC512x_CLK_REF>, 145 <&clks MPC512x_CLK_MSCAN1_MCLK>; 146 clock-names = "ipg", "ips", "sys", "ref", "mclk"; 147 }; 148 149 sdhc@1500 { 150 compatible = "fsl,mpc5121-sdhc"; 151 interrupts = <8 0x8>; 152 reg = <0x1500 0x100>; 153 clocks = <&clks MPC512x_CLK_IPS>, 154 <&clks MPC512x_CLK_SDHC>; 155 clock-names = "ipg", "per"; 156 }; 157 158 i2c@1700 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 162 reg = <0x1700 0x20>; 163 interrupts = <0x9 0x8>; 164 clocks = <&clks MPC512x_CLK_I2C>; 165 clock-names = "ipg"; 166 }; 167 168 i2c@1720 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 172 reg = <0x1720 0x20>; 173 interrupts = <0xa 0x8>; 174 clocks = <&clks MPC512x_CLK_I2C>; 175 clock-names = "ipg"; 176 }; 177 178 i2c@1740 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 182 reg = <0x1740 0x20>; 183 interrupts = <0xb 0x8>; 184 clocks = <&clks MPC512x_CLK_I2C>; 185 clock-names = "ipg"; 186 }; 187 188 i2ccontrol@1760 { 189 compatible = "fsl,mpc5121-i2c-ctrl"; 190 reg = <0x1760 0x8>; 191 }; 192 193 diu@2100 { 194 compatible = "fsl,mpc5121-diu"; 195 reg = <0x2100 0x100>; 196 interrupts = <64 0x8>; 197 clocks = <&clks MPC512x_CLK_DIU>; 198 clock-names = "ipg"; 199 }; 200 201 mdio@2800 { 202 compatible = "fsl,mpc5121-fec-mdio"; 203 reg = <0x2800 0x800>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 phy0: ethernet-phy@0 { 207 reg = <1>; 208 }; 209 }; 210 211 eth0: ethernet@2800 { 212 compatible = "fsl,mpc5125-fec"; 213 reg = <0x2800 0x800>; 214 local-mac-address = [ 00 00 00 00 00 00 ]; 215 interrupts = <4 0x8>; 216 phy-handle = < &phy0 >; 217 phy-connection-type = "rmii"; 218 clocks = <&clks MPC512x_CLK_FEC>; 219 clock-names = "per"; 220 }; 221 222 // IO control 223 ioctl@a000 { 224 compatible = "fsl,mpc5125-ioctl"; 225 reg = <0xA000 0x1000>; 226 }; 227 228 // disable USB1 port 229 // TODO: 230 // correct pinmux config and fix USB3320 ulpi dependency 231 // before re-enabling it 232 usb@3000 { 233 compatible = "fsl,mpc5121-usb2-dr"; 234 reg = <0x3000 0x400>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <43 0x8>; 238 dr_mode = "host"; 239 phy_type = "ulpi"; 240 clocks = <&clks MPC512x_CLK_USB1>; 241 clock-names = "ipg"; 242 status = "disabled"; 243 }; 244 245 sclpc@10100 { 246 compatible = "fsl,mpc512x-lpbfifo"; 247 reg = <0x10100 0x50>; 248 interrupts = <7 0x8>; 249 dmas = <&dma0 26>; 250 dma-names = "rx-tx"; 251 }; 252 253 // 5125 PSCs are not 52xx or 5121 PSC compatible 254 // PSC1 uart0 aka ttyPSC0 255 serial@11100 { 256 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 257 reg = <0x11100 0x100>; 258 interrupts = <40 0x8>; 259 fsl,rx-fifo-size = <16>; 260 fsl,tx-fifo-size = <16>; 261 clocks = <&clks MPC512x_CLK_PSC1>, 262 <&clks MPC512x_CLK_PSC1_MCLK>; 263 clock-names = "ipg", "mclk"; 264 }; 265 266 // PSC9 uart1 aka ttyPSC1 267 serial@11900 { 268 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc"; 269 reg = <0x11900 0x100>; 270 interrupts = <40 0x8>; 271 fsl,rx-fifo-size = <16>; 272 fsl,tx-fifo-size = <16>; 273 clocks = <&clks MPC512x_CLK_PSC9>, 274 <&clks MPC512x_CLK_PSC9_MCLK>; 275 clock-names = "ipg", "mclk"; 276 }; 277 278 pscfifo@11f00 { 279 compatible = "fsl,mpc5121-psc-fifo"; 280 reg = <0x11f00 0x100>; 281 interrupts = <40 0x8>; 282 clocks = <&clks MPC512x_CLK_PSC_FIFO>; 283 clock-names = "ipg"; 284 }; 285 286 dma0: dma@14000 { 287 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2" 288 reg = <0x14000 0x1800>; 289 interrupts = <65 0x8>; 290 #dma-cells = <1>; 291 }; 292 }; 293}; 294