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Searched +full:0 +full:x1600 (Results 1 – 25 of 63) sorted by relevance

123

/freebsd/sys/dev/drm2/
H A Ddrm_edid_modes.h36 736, 832, 0, 350, 382, 385, 445, 0,
40 736, 832, 0, 400, 401, 404, 445, 0,
44 828, 936, 0, 400, 401, 404, 446, 0,
48 752, 800, 0, 480, 489, 492, 525, 0,
52 704, 832, 0, 480, 489, 492, 520, 0,
56 720, 840, 0, 480, 481, 484, 500, 0,
60 752, 832, 0, 480, 481, 484, 509, 0,
64 896, 1024, 0, 600, 601, 603, 625, 0,
68 968, 1056, 0, 600, 601, 605, 628, 0,
72 976, 1040, 0, 600, 637, 643, 666, 0,
[all …]
H A Ddrm_pciids.h14 {0, 0, 0, NULL}
17 {0x3D3D, 0x0008, 0, "3DLabs GLINT Gamma G1"}, \
18 {0, 0, 0, NULL}
21 {0x8086, 0x1132, 0, "Intel i815 GMCH"}, \
22 {0x8086, 0x7121, 0, "Intel i810 GMCH"}, \
23 {0x8086, 0x7123, 0, "Intel i810-DC100 GMCH"}, \
24 {0x8086, 0x7125, 0, "Intel i810E GMCH"}, \
25 {0, 0, 0, NULL}
28 {0x8086, 0x2562, 0, "Intel i845G GMCH"}, \
29 {0x8086, 0x2572, 0, "Intel i865G GMCH"}, \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-edp-legacy.yaml67 # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
73 # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
104 hsync-active = <0>;
109 vsync-active = <0>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dingenic,mac.yaml20 - ingenic,x1600-mac
66 reg = <0x134b0000 0x2000>;
H A Dsnps,dwmac.yaml64 - ingenic,x1600-mac
218 "^queue[0-9]$":
356 "^queue[0-9]$":
370 Queue 0 is reserved for legacy traffic and so no AVB is
618 - ingenic,x1600-mac
644 reg = <0xe0800000 0x8000>;
662 snps,wr_osr_lmt = <0xf>;
663 snps,rd_osr_lmt = <0xf>;
664 snps,blen = <256 128 64 32 0 0 0>;
672 snps,map-to-dma-channel = <0x0>;
[all …]
/freebsd/sys/powerpc/powermac/
H A Dviareg.h32 #define vBufB 0x0000 /* register B */
33 #define vDirB 0x0400 /* data direction register */
34 #define vDirA 0x0600 /* data direction register */
35 #define vT1C 0x0800 /* Timer 1 counter Lo */
36 #define vT1CH 0x0a00 /* Timer 1 counter Hi */
37 #define vSR 0x1400 /* shift register */
38 #define vACR 0x1600 /* aux control register */
39 #define vPCR 0x1800 /* peripheral control register */
40 #define vIFR 0x1a00 /* interrupt flag register */
41 #define vIER 0x1c00 /* interrupt enable register */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc2.yaml24 - const: ingenic,x1600-otg
197 reg = <0x10180000 0x40000>;
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dpm8916.dtsi17 hysteresis = <0>;
23 hysteresis = <0>;
29 hysteresis = <0>;
38 pm8916_0: pmic@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
47 mode-bootloader = <0x2>;
48 mode-recovery = <0x1>;
52 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
/freebsd/sys/dev/ae/
H A Dif_aereg.h31 #define AE_MASTER_REG 0x1400
33 #define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
34 #define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
35 #define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
36 #define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
38 #define AE_MASTER_REVNUM_MASK 0xff
40 #define AE_MASTER_DEVID_MASK 0xff
45 #define AE_ISR_REG 0x1600
46 #define AE_ISR_TIMER 0x00000001 /* Counter expired. */
47 #define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
[all …]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/sys/dev/mge/
H A Dif_mgevar.h43 #define MGE_RX_DEFAULT_QUEUE 0
48 #define MGE_IC_RX 0
119 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))
120 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))
126 } while (0)
134 } while (0)
144 } while (0)
149 } while (0)
154 } while (0)
159 } while (0)
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_swp.h44 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80)
67 #define DPAA2_SWP_REV_4000 0x04000000
68 #define DPAA2_SWP_REV_4100 0x04010000
69 #define DPAA2_SWP_REV_4101 0x04010001
70 #define DPAA2_SWP_REV_5000 0x05000000
72 #define DPAA2_SWP_REV_MASK 0xFFFF0000
75 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/
76 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */
77 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */
78 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap54xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
21 reg = <0x0108>;
25 #clock-cells = <0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
44 reg = <0x0108>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
62 #clock-cells = <0>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
73 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
75 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
77 (((addr)[0] & (addr)[1] & (addr)[2] & \
78 (addr)[3] & (addr)[4] & (addr)[5]) == 0xf
[all...]
/freebsd/sys/contrib/dev/rtw88/
H A Dmac80211.c77 int ret = 0; in rtw_ops_config()
109 [0] = {
110 .mac_addr = {.addr = 0x0610},
111 .bssid = {.addr = 0x0618},
112 .net_type = {.addr = 0x0100, .mask = 0x30000},
113 .aid = {.addr = 0x06a8, .mask = 0x7ff},
114 .bcn_ctrl = {.addr = 0x0550, .mask = 0xf
[all...]
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore.h43 #define ECORE_ENGINEERING_VERSION 0
84 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
114 } while (0)
126 } while (0)
155 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
168 } while (0)
179 } while (0)
189 } while (0)
200 } while (0)
204 ECORE_LEVEL_VERBOSE = 0x0,
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/i386/i386/
H A Dinitcpu.c73 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
76 * 0: keep enable CLFLUSH
98 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ in init_bluelightning()
100 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ in init_bluelightning()
102 /* Enables 13MB and 0-640KB cache. */ in init_bluelightning()
103 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); in init_bluelightning()
105 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ in init_bluelightning()
107 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ in init_bluelightning()
111 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ in init_bluelightning()
151 write_cyrix_reg(0, 0); /* dummy write */ in init_486dlc()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82541.c79 sizeof(e1000_igp_cable_length_table[0]))
187 * if size != 0, it can be added to a constant and become in e1000_init_nvm_params_82541()
303 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); in e1000_reset_hw_82541()
305 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_82541()
360 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); in e1000_reset_hw_82541()
405 for (i = 0; i < mac->mta_reg_count; i++) { in e1000_init_hw_82541()
406 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_82541()
419 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_82541()
422 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_82541()
608 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); in e1000_check_for_link_82541()
[all …]

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