Lines Matching +full:0 +full:x1600

43 #define ECORE_ENGINEERING_VERSION	0
84 	ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
114 } while (0)
126 } while (0)
155 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
168 } while (0)
179 } while (0)
189 } while (0)
200 } while (0)
204 	ECORE_LEVEL_VERBOSE	= 0x0,
205 	ECORE_LEVEL_INFO	= 0x1,
206 	ECORE_LEVEL_NOTICE	= 0x2,
207 	ECORE_LEVEL_ERR		= 0x3,
211 #define ECORE_LOG_VERBOSE_MASK	(0x3fffffff)
212 #define ECORE_LOG_INFO_MASK	(0x40000000)
213 #define ECORE_LOG_NOTICE_MASK	(0x80000000)
217 	ECORE_MSG_DRV		= 0x0001,
218 	ECORE_MSG_PROBE		= 0x0002,
219 	ECORE_MSG_LINK		= 0x0004,
220 	ECORE_MSG_TIMER		= 0x0008,
221 	ECORE_MSG_IFDOWN	= 0x0010,
222 	ECORE_MSG_IFUP		= 0x0020,
223 	ECORE_MSG_RX_ERR	= 0x0040,
224 	ECORE_MSG_TX_ERR	= 0x0080,
225 	ECORE_MSG_TX_QUEUED	= 0x0100,
226 	ECORE_MSG_INTR		= 0x0200,
227 	ECORE_MSG_TX_DONE	= 0x0400,
228 	ECORE_MSG_RX_STATUS	= 0x0800,
229 	ECORE_MSG_PKTDATA	= 0x1000,
230 	ECORE_MSG_HW		= 0x2000,
231 	ECORE_MSG_WOL		= 0x4000,
233 	ECORE_MSG_SPQ		= 0x10000,
234 	ECORE_MSG_STATS		= 0x20000,
235 	ECORE_MSG_DCB		= 0x40000,
236 	ECORE_MSG_IOV		= 0x80000,
237 	ECORE_MSG_SP		= 0x100000,
238 	ECORE_MSG_STORAGE	= 0x200000,
239 	ECORE_MSG_OOO		= 0x200000,
240 	ECORE_MSG_CXT		= 0x800000,
241 	ECORE_MSG_LL2		= 0x1000000,
242 	ECORE_MSG_ILT		= 0x2000000,
243 	ECORE_MSG_RDMA		= 0x4000000,
244 	ECORE_MSG_DEBUG		= 0x8000000,
245 	/* to be added...up to 0x8000000 */
249 #define for_each_hwfn(p_dev, i)	for (i = 0; i < p_dev->num_hwfns; i++)
368 	 * In case of legacy MFW, would be set to `0'.
508 #define DMAE_MAX_RW_SIZE	0x2000
654 	(ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
814 #define ECORE_DEV_ID_MASK	0xff00
815 #define ECORE_DEV_ID_MASK_BB	0x1600
816 #define ECORE_DEV_ID_MASK_AH	0x8000
817 #define ECORE_DEV_ID_MASK_E5	0x8100
820 #define CHIP_NUM_MASK			0xffff
821 #define CHIP_NUM_SHIFT			0
824 #define CHIP_REV_MASK			0xf
825 #define CHIP_REV_SHIFT			0
827 #define CHIP_REV_IS_TEDIBEAR(_p_dev)	((_p_dev)->chip_rev == 0x5)
828 #define CHIP_REV_IS_EMUL_A0(_p_dev)	((_p_dev)->chip_rev == 0xe)
829 #define CHIP_REV_IS_EMUL_B0(_p_dev)	((_p_dev)->chip_rev == 0xc)
832 #define CHIP_REV_IS_FPGA_A0(_p_dev)	((_p_dev)->chip_rev == 0xf)
833 #define CHIP_REV_IS_FPGA_B0(_p_dev)	((_p_dev)->chip_rev == 0xd)
853 #define CHIP_METAL_MASK			0xff
854 #define CHIP_METAL_SHIFT		0
857 #define CHIP_BOND_ID_MASK		0xff
858 #define CHIP_BOND_ID_SHIFT		0
907 #define ECORE_LEADING_HWFN(dev)		(&dev->hwfns[0])
923 	/* Macro for getting the index (0/1) of the engine-affinitized hwfn */
925 	(IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
1021 #define PQ_FLAGS_RLS	(1 << 0)