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/linux/arch/arm/boot/dts/vt8500/
H A Dwm8505.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
43 reg = <0xd8140000 0x10000>;
52 reg = <0xD8150000 0x10000>;
58 reg = <0xd8110000 0x10000>;
67 reg = <0xd8120000 0x4>;
72 reg = <0xd8130000 0x1000>;
75 #size-cells = <0>;
78 #clock-cells = <0>;
[all …]
H A Dvt8500.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
41 reg = <0xd8140000 0x10000>;
47 reg = <0xd8110000 0x10000>;
56 reg = <0xd8120000 0x4>;
61 reg = <0xd8130000 0x1000>;
65 #size-cells = <0>;
68 #clock-cells = <0>;
74 #clock-cells = <0>;
[all …]
H A Dwm8750.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
45 reg = <0xd8140000 0x10000>;
54 reg = <0xD8150000 0x10000>;
60 reg = <0xd8110000 0x10000>;
69 reg = <0xd8120000 0x4>;
74 reg = <0xd8130000 0x1000>;
78 #size-cells = <0>;
81 #clock-cells = <0>;
[all …]
H A Dwm8850.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
42 reg = <0xd8140000 0x10000>;
51 reg = <0xD8150000 0x10000>;
57 reg = <0xd8110000 0x10000>;
66 reg = <0xd8120000 0x4>;
71 reg = <0xd8130000 0x1000>;
75 #size-cells = <0>;
78 #clock-cells = <0>;
[all …]
H A Dwm8650.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
39 reg = <0xd8140000 0x10000>;
48 reg = <0xD8150000 0x10000>;
54 reg = <0xd8110000 0x10000>;
63 reg = <0xd8120000 0x4>;
68 reg = <0xd8130000 0x1000>;
72 #size-cells = <0>;
75 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Dvia,vt8500-uart.yaml43 reg = <0xd8200000 0x1040>;
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_0_offset.h25 #define mmUMCCH0_0_EccCtrl 0x0053
26 #define mmUMCCH0_0_EccCtrl_BASE_IDX 0
27 #define mmUMCCH1_0_EccCtrl 0x0853
28 #define mmUMCCH1_0_EccCtrl_BASE_IDX 0
29 #define mmUMCCH2_0_EccCtrl 0x1053
30 #define mmUMCCH2_0_EccCtrl_BASE_IDX 0
31 #define mmUMCCH3_0_EccCtrl 0x1853
32 #define mmUMCCH3_0_EccCtrl_BASE_IDX 0
34 #define mmUMCCH0_0_UMC_CONFIG 0x0040
35 #define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,xspi.yaml80 #size-cells = <0>;
82 reg = <0x0 0xa0010000 0x0 0x1040>,
83 <0x0 0xb0000000 0x0 0x1000>,
84 <0x0 0xa0020000 0x0 0x100>;
86 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
89 flash@0 {
92 reg = <0>;
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
H A Dqcom,msm8998-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
79 reg = <0x0c900000 0x1000>;
93 iommus = <&mmss_smmu 0>;
100 reg = <0x0c901000 0x8f000>,
101 <0x0c9a8e00 0xf0>,
102 <0x0c9b0000 0x2008>,
103 <0x0c9b8000 0x1040>;
114 interrupts = <0>;
[all …]
/linux/drivers/virtio/
H A Dvirtio_pci_modern_dev.c112 * Returns offset of the capability, or 0.
120 pos > 0; in virtio_pci_find_capability()
142 return 0; in virtio_pci_find_capability()
221 * Return 0 on succeed otherwise fail
235 if (devid < 0) in vp_modern_probe()
239 /* We only own devices >= 0x1000 and <= 0x107f: leave the rest. */ in vp_modern_probe()
240 if (pci_dev->device < 0x1000 || pci_dev->device > 0x107f) in vp_modern_probe()
243 if (pci_dev->device < 0x1040) { in vp_modern_probe()
249 /* Modern devices: simply use PCI device id, but start from 0x1040. */ in vp_modern_probe()
250 mdev->id.device = pci_dev->device - 0x1040; in vp_modern_probe()
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1.dtsi18 #clock-cells = <0>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
26 reg = <0>;
37 #address-cells = <0>;
44 ranges = <0x0 0x1fd00000 0x130000>;
48 reg = <0x1040 0x18>;
57 reg = <0x1058 0x18>;
66 reg = <0x1070 0x18>;
75 reg = <0x1088 0x18>;
[all …]
/linux/Documentation/scsi/
H A Dhptiop.rst16 0x11C5C Link Interface IRQ Set
17 0x11C60 Link Interface IRQ Clear
23 0x10 Inbound Message Register 0
24 0x14 Inbound Message Register 1
25 0x18 Outbound Message Register 0
26 0x1C Outbound Message Register 1
27 0x20 Inbound Doorbell Register
28 0x24 Inbound Interrupt Status Register
29 0x28 Inbound Interrupt Mask Register
30 0x30 Outbound Interrupt Status Register
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
H A Dreg.h14 #define RVU_PF_DISC (0x0)
15 #define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16)
16 #define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12)
20 #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4)
21 #define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4)
22 #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3)
23 #define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6)
24 #define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6)
25 #define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0x2990 | (a) << 6)
26 #define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0x2998 | (a) << 6)
[all …]
/linux/lib/crc/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/linux/include/linux/mtd/
H A Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos-pcie.c18 #define PCIE_PHY_OFFSET(x) ((x) * 0x4)
21 #define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
22 #define PCIE_MAC_RESET_MASK 0xFF
24 #define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
25 #define PCIE_REFCLK_GATING_EN BIT(0)
26 #define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
27 #define PCIE_PHY_RESET BIT(0)
28 #define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
29 #define PCIE_GLOBAL_RESET BIT(0)
31 #define PCIE_REFCLK_MASK 0x16
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.h9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10 #define ADF_RING_CSR_RING_CONFIG 0x1000
11 #define ADF_RING_CSR_RING_LBASE 0x1040
12 #define ADF_RING_CSR_RING_UBASE 0x1080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_STAT 0x140
16 #define ADF_RING_CSR_UO_STAT 0x148
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_NE_STAT 0x150
[all …]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson_regs.h25 "parse_r __res,%0\n\t" in read_cpucfg()
29 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" in read_cpucfg()
38 #define LOONGSON_CFG0 0x0
39 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
41 #define LOONGSON_CFG1 0x1
42 #define LOONGSON_CFG1_FP BIT(0)
74 #define LOONGSON_CFG2 0x2
75 #define LOONGSON_CFG2_LEXT1 BIT(0)
104 #define LOONGSON_CFG3 0x3
105 #define LOONGSON_CFG3_LCAMP BIT(0)
[all …]
/linux/drivers/misc/mei/
H A Dhw-txe-regs.h30 #define PCI_CFG_TXE_FW_STS0 0x40
31 # define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F
32 # define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C0
33 # define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
34 # define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F000
35 # define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F0000
36 # define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F00000
37 #define PCI_CFG_TXE_FW_STS1 0x48
39 #define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */
42 #define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc-sm6350.c36 { 249600000, 2000000000, 0 },
40 .l = 0x3a,
41 .alpha = 0x5555,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002067,
44 .test_ctl_val = 0x40000000,
45 .test_ctl_hi_val = 0x00000002,
46 .user_ctl_val = 0x00000000,
47 .user_ctl_hi_val = 0x00004805,
51 .offset = 0x0,
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]

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