1*ac69461bSMauro Carvalho Chehab.. SPDX-License-Identifier: GPL-2.0 2*ac69461bSMauro Carvalho Chehab.. include:: <isonum.txt> 3*ac69461bSMauro Carvalho Chehab 4*ac69461bSMauro Carvalho Chehab====================================================== 5*ac69461bSMauro Carvalho ChehabHighpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop) 6*ac69461bSMauro Carvalho Chehab====================================================== 7*ac69461bSMauro Carvalho Chehab 8*ac69461bSMauro Carvalho ChehabController Register Map 9*ac69461bSMauro Carvalho Chehab----------------------- 10*ac69461bSMauro Carvalho Chehab 11*ac69461bSMauro Carvalho ChehabFor RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2 12*ac69461bSMauro Carvalho Chehab 13*ac69461bSMauro Carvalho Chehab ============== ================================== 14*ac69461bSMauro Carvalho Chehab BAR0 offset Register 15*ac69461bSMauro Carvalho Chehab ============== ================================== 16*ac69461bSMauro Carvalho Chehab 0x11C5C Link Interface IRQ Set 17*ac69461bSMauro Carvalho Chehab 0x11C60 Link Interface IRQ Clear 18*ac69461bSMauro Carvalho Chehab ============== ================================== 19*ac69461bSMauro Carvalho Chehab 20*ac69461bSMauro Carvalho Chehab ============== ================================== 21*ac69461bSMauro Carvalho Chehab BAR2 offset Register 22*ac69461bSMauro Carvalho Chehab ============== ================================== 23*ac69461bSMauro Carvalho Chehab 0x10 Inbound Message Register 0 24*ac69461bSMauro Carvalho Chehab 0x14 Inbound Message Register 1 25*ac69461bSMauro Carvalho Chehab 0x18 Outbound Message Register 0 26*ac69461bSMauro Carvalho Chehab 0x1C Outbound Message Register 1 27*ac69461bSMauro Carvalho Chehab 0x20 Inbound Doorbell Register 28*ac69461bSMauro Carvalho Chehab 0x24 Inbound Interrupt Status Register 29*ac69461bSMauro Carvalho Chehab 0x28 Inbound Interrupt Mask Register 30*ac69461bSMauro Carvalho Chehab 0x30 Outbound Interrupt Status Register 31*ac69461bSMauro Carvalho Chehab 0x34 Outbound Interrupt Mask Register 32*ac69461bSMauro Carvalho Chehab 0x40 Inbound Queue Port 33*ac69461bSMauro Carvalho Chehab 0x44 Outbound Queue Port 34*ac69461bSMauro Carvalho Chehab ============== ================================== 35*ac69461bSMauro Carvalho Chehab 36*ac69461bSMauro Carvalho ChehabFor Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: 37*ac69461bSMauro Carvalho Chehab 38*ac69461bSMauro Carvalho Chehab ============== ================================== 39*ac69461bSMauro Carvalho Chehab BAR0 offset Register 40*ac69461bSMauro Carvalho Chehab ============== ================================== 41*ac69461bSMauro Carvalho Chehab 0x10 Inbound Message Register 0 42*ac69461bSMauro Carvalho Chehab 0x14 Inbound Message Register 1 43*ac69461bSMauro Carvalho Chehab 0x18 Outbound Message Register 0 44*ac69461bSMauro Carvalho Chehab 0x1C Outbound Message Register 1 45*ac69461bSMauro Carvalho Chehab 0x20 Inbound Doorbell Register 46*ac69461bSMauro Carvalho Chehab 0x24 Inbound Interrupt Status Register 47*ac69461bSMauro Carvalho Chehab 0x28 Inbound Interrupt Mask Register 48*ac69461bSMauro Carvalho Chehab 0x30 Outbound Interrupt Status Register 49*ac69461bSMauro Carvalho Chehab 0x34 Outbound Interrupt Mask Register 50*ac69461bSMauro Carvalho Chehab 0x40 Inbound Queue Port 51*ac69461bSMauro Carvalho Chehab 0x44 Outbound Queue Port 52*ac69461bSMauro Carvalho Chehab ============== ================================== 53*ac69461bSMauro Carvalho Chehab 54*ac69461bSMauro Carvalho ChehabFor Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: 55*ac69461bSMauro Carvalho Chehab 56*ac69461bSMauro Carvalho Chehab ============== ================================== 57*ac69461bSMauro Carvalho Chehab BAR0 offset Register 58*ac69461bSMauro Carvalho Chehab ============== ================================== 59*ac69461bSMauro Carvalho Chehab 0x20400 Inbound Doorbell Register 60*ac69461bSMauro Carvalho Chehab 0x20404 Inbound Interrupt Mask Register 61*ac69461bSMauro Carvalho Chehab 0x20408 Outbound Doorbell Register 62*ac69461bSMauro Carvalho Chehab 0x2040C Outbound Interrupt Mask Register 63*ac69461bSMauro Carvalho Chehab ============== ================================== 64*ac69461bSMauro Carvalho Chehab 65*ac69461bSMauro Carvalho Chehab ============== ================================== 66*ac69461bSMauro Carvalho Chehab BAR1 offset Register 67*ac69461bSMauro Carvalho Chehab ============== ================================== 68*ac69461bSMauro Carvalho Chehab 0x0 Inbound Queue Head Pointer 69*ac69461bSMauro Carvalho Chehab 0x4 Inbound Queue Tail Pointer 70*ac69461bSMauro Carvalho Chehab 0x8 Outbound Queue Head Pointer 71*ac69461bSMauro Carvalho Chehab 0xC Outbound Queue Tail Pointer 72*ac69461bSMauro Carvalho Chehab 0x10 Inbound Message Register 73*ac69461bSMauro Carvalho Chehab 0x14 Outbound Message Register 74*ac69461bSMauro Carvalho Chehab 0x40-0x1040 Inbound Queue 75*ac69461bSMauro Carvalho Chehab 0x1040-0x2040 Outbound Queue 76*ac69461bSMauro Carvalho Chehab ============== ================================== 77*ac69461bSMauro Carvalho Chehab 78*ac69461bSMauro Carvalho ChehabFor Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: 79*ac69461bSMauro Carvalho Chehab 80*ac69461bSMauro Carvalho Chehab ============== ================================== 81*ac69461bSMauro Carvalho Chehab BAR0 offset Register 82*ac69461bSMauro Carvalho Chehab ============== ================================== 83*ac69461bSMauro Carvalho Chehab 0x0 IOP configuration information. 84*ac69461bSMauro Carvalho Chehab ============== ================================== 85*ac69461bSMauro Carvalho Chehab 86*ac69461bSMauro Carvalho Chehab ============== =================================================== 87*ac69461bSMauro Carvalho Chehab BAR1 offset Register 88*ac69461bSMauro Carvalho Chehab ============== =================================================== 89*ac69461bSMauro Carvalho Chehab 0x4000 Inbound List Base Address Low 90*ac69461bSMauro Carvalho Chehab 0x4004 Inbound List Base Address High 91*ac69461bSMauro Carvalho Chehab 0x4018 Inbound List Write Pointer 92*ac69461bSMauro Carvalho Chehab 0x402C Inbound List Configuration and Control 93*ac69461bSMauro Carvalho Chehab 0x4050 Outbound List Base Address Low 94*ac69461bSMauro Carvalho Chehab 0x4054 Outbound List Base Address High 95*ac69461bSMauro Carvalho Chehab 0x4058 Outbound List Copy Pointer Shadow Base Address Low 96*ac69461bSMauro Carvalho Chehab 0x405C Outbound List Copy Pointer Shadow Base Address High 97*ac69461bSMauro Carvalho Chehab 0x4088 Outbound List Interrupt Cause 98*ac69461bSMauro Carvalho Chehab 0x408C Outbound List Interrupt Enable 99*ac69461bSMauro Carvalho Chehab 0x1020C PCIe Function 0 Interrupt Enable 100*ac69461bSMauro Carvalho Chehab 0x10400 PCIe Function 0 to CPU Message A 101*ac69461bSMauro Carvalho Chehab 0x10420 CPU to PCIe Function 0 Message A 102*ac69461bSMauro Carvalho Chehab 0x10480 CPU to PCIe Function 0 Doorbell 103*ac69461bSMauro Carvalho Chehab 0x10484 CPU to PCIe Function 0 Doorbell Enable 104*ac69461bSMauro Carvalho Chehab ============== =================================================== 105*ac69461bSMauro Carvalho Chehab 106*ac69461bSMauro Carvalho Chehab 107*ac69461bSMauro Carvalho ChehabI/O Request Workflow of Not Marvell Frey 108*ac69461bSMauro Carvalho Chehab---------------------------------------- 109*ac69461bSMauro Carvalho Chehab 110*ac69461bSMauro Carvalho ChehabAll queued requests are handled via inbound/outbound queue port. 111*ac69461bSMauro Carvalho ChehabA request packet can be allocated in either IOP or host memory. 112*ac69461bSMauro Carvalho Chehab 113*ac69461bSMauro Carvalho ChehabTo send a request to the controller: 114*ac69461bSMauro Carvalho Chehab 115*ac69461bSMauro Carvalho Chehab - Get a free request packet by reading the inbound queue port or 116*ac69461bSMauro Carvalho Chehab allocate a free request in host DMA coherent memory. 117*ac69461bSMauro Carvalho Chehab 118*ac69461bSMauro Carvalho Chehab The value returned from the inbound queue port is an offset 119*ac69461bSMauro Carvalho Chehab relative to the IOP BAR0. 120*ac69461bSMauro Carvalho Chehab 121*ac69461bSMauro Carvalho Chehab Requests allocated in host memory must be aligned on 32-bytes boundary. 122*ac69461bSMauro Carvalho Chehab 123*ac69461bSMauro Carvalho Chehab - Fill the packet. 124*ac69461bSMauro Carvalho Chehab 125*ac69461bSMauro Carvalho Chehab - Post the packet to IOP by writing it to inbound queue. For requests 126*ac69461bSMauro Carvalho Chehab allocated in IOP memory, write the offset to inbound queue port. For 127*ac69461bSMauro Carvalho Chehab requests allocated in host memory, write (0x80000000|(bus_addr>>5)) 128*ac69461bSMauro Carvalho Chehab to the inbound queue port. 129*ac69461bSMauro Carvalho Chehab 130*ac69461bSMauro Carvalho Chehab - The IOP process the request. When the request is completed, it 131*ac69461bSMauro Carvalho Chehab will be put into outbound queue. An outbound interrupt will be 132*ac69461bSMauro Carvalho Chehab generated. 133*ac69461bSMauro Carvalho Chehab 134*ac69461bSMauro Carvalho Chehab For requests allocated in IOP memory, the request offset is posted to 135*ac69461bSMauro Carvalho Chehab outbound queue. 136*ac69461bSMauro Carvalho Chehab 137*ac69461bSMauro Carvalho Chehab For requests allocated in host memory, (0x80000000|(bus_addr>>5)) 138*ac69461bSMauro Carvalho Chehab is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT 139*ac69461bSMauro Carvalho Chehab flag is set in the request, the low 32-bit context value will be 140*ac69461bSMauro Carvalho Chehab posted instead. 141*ac69461bSMauro Carvalho Chehab 142*ac69461bSMauro Carvalho Chehab - The host read the outbound queue and complete the request. 143*ac69461bSMauro Carvalho Chehab 144*ac69461bSMauro Carvalho Chehab For requests allocated in IOP memory, the host driver free the request 145*ac69461bSMauro Carvalho Chehab by writing it to the outbound queue. 146*ac69461bSMauro Carvalho Chehab 147*ac69461bSMauro Carvalho ChehabNon-queued requests (reset/flush etc) can be sent via inbound message 148*ac69461bSMauro Carvalho Chehabregister 0. An outbound message with the same value indicates the completion 149*ac69461bSMauro Carvalho Chehabof an inbound message. 150*ac69461bSMauro Carvalho Chehab 151*ac69461bSMauro Carvalho Chehab 152*ac69461bSMauro Carvalho ChehabI/O Request Workflow of Marvell Frey 153*ac69461bSMauro Carvalho Chehab------------------------------------ 154*ac69461bSMauro Carvalho Chehab 155*ac69461bSMauro Carvalho ChehabAll queued requests are handled via inbound/outbound list. 156*ac69461bSMauro Carvalho Chehab 157*ac69461bSMauro Carvalho ChehabTo send a request to the controller: 158*ac69461bSMauro Carvalho Chehab 159*ac69461bSMauro Carvalho Chehab - Allocate a free request in host DMA coherent memory. 160*ac69461bSMauro Carvalho Chehab 161*ac69461bSMauro Carvalho Chehab Requests allocated in host memory must be aligned on 32-bytes boundary. 162*ac69461bSMauro Carvalho Chehab 163*ac69461bSMauro Carvalho Chehab - Fill the request with index of the request in the flag. 164*ac69461bSMauro Carvalho Chehab 165*ac69461bSMauro Carvalho Chehab Fill a free inbound list unit with the physical address and the size of 166*ac69461bSMauro Carvalho Chehab the request. 167*ac69461bSMauro Carvalho Chehab 168*ac69461bSMauro Carvalho Chehab Set up the inbound list write pointer with the index of previous unit, 169*ac69461bSMauro Carvalho Chehab round to 0 if the index reaches the supported count of requests. 170*ac69461bSMauro Carvalho Chehab 171*ac69461bSMauro Carvalho Chehab - Post the inbound list writer pointer to IOP. 172*ac69461bSMauro Carvalho Chehab 173*ac69461bSMauro Carvalho Chehab - The IOP process the request. When the request is completed, the flag of 174*ac69461bSMauro Carvalho Chehab the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a 175*ac69461bSMauro Carvalho Chehab free outbound list unit and the index of the outbound list unit will be 176*ac69461bSMauro Carvalho Chehab put into the copy pointer shadow register. An outbound interrupt will be 177*ac69461bSMauro Carvalho Chehab generated. 178*ac69461bSMauro Carvalho Chehab 179*ac69461bSMauro Carvalho Chehab - The host read the outbound list copy pointer shadow register and compare 180*ac69461bSMauro Carvalho Chehab with previous saved read pointer N. If they are different, the host will 181*ac69461bSMauro Carvalho Chehab read the (N+1)th outbound list unit. 182*ac69461bSMauro Carvalho Chehab 183*ac69461bSMauro Carvalho Chehab The host get the index of the request from the (N+1)th outbound list 184*ac69461bSMauro Carvalho Chehab unit and complete the request. 185*ac69461bSMauro Carvalho Chehab 186*ac69461bSMauro Carvalho ChehabNon-queued requests (reset communication/reset/flush etc) can be sent via PCIe 187*ac69461bSMauro Carvalho ChehabFunction 0 to CPU Message A register. The CPU to PCIe Function 0 Message register 188*ac69461bSMauro Carvalho Chehabwith the same value indicates the completion of message. 189*ac69461bSMauro Carvalho Chehab 190*ac69461bSMauro Carvalho Chehab 191*ac69461bSMauro Carvalho ChehabUser-level Interface 192*ac69461bSMauro Carvalho Chehab--------------------- 193*ac69461bSMauro Carvalho Chehab 194*ac69461bSMauro Carvalho ChehabThe driver exposes following sysfs attributes: 195*ac69461bSMauro Carvalho Chehab 196*ac69461bSMauro Carvalho Chehab ================== === ======================== 197*ac69461bSMauro Carvalho Chehab NAME R/W Description 198*ac69461bSMauro Carvalho Chehab ================== === ======================== 199*ac69461bSMauro Carvalho Chehab driver-version R driver version string 200*ac69461bSMauro Carvalho Chehab firmware-version R firmware version string 201*ac69461bSMauro Carvalho Chehab ================== === ======================== 202*ac69461bSMauro Carvalho Chehab 203*ac69461bSMauro Carvalho Chehab 204*ac69461bSMauro Carvalho Chehab----------------------------------------------------------------------------- 205*ac69461bSMauro Carvalho Chehab 206*ac69461bSMauro Carvalho ChehabCopyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. 207*ac69461bSMauro Carvalho Chehab 208*ac69461bSMauro Carvalho Chehab This file is distributed in the hope that it will be useful, 209*ac69461bSMauro Carvalho Chehab but WITHOUT ANY WARRANTY; without even the implied warranty of 210*ac69461bSMauro Carvalho Chehab MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 211*ac69461bSMauro Carvalho Chehab GNU General Public License for more details. 212*ac69461bSMauro Carvalho Chehab 213*ac69461bSMauro Carvalho Chehab linux@highpoint-tech.com 214*ac69461bSMauro Carvalho Chehab 215*ac69461bSMauro Carvalho Chehab http://www.highpoint-tech.com 216