1e53ee4acSSai Krishna /* SPDX-License-Identifier: GPL-2.0 */ 2e53ee4acSSai Krishna /* Marvell RVU Admin Function driver 3e53ee4acSSai Krishna * 4e53ee4acSSai Krishna * Copyright (C) 2024 Marvell. 5e53ee4acSSai Krishna * 6e53ee4acSSai Krishna */ 7e53ee4acSSai Krishna 8e53ee4acSSai Krishna #ifndef RVU_MBOX_REG_H 9e53ee4acSSai Krishna #define RVU_MBOX_REG_H 10e53ee4acSSai Krishna #include "../rvu.h" 11e53ee4acSSai Krishna #include "../rvu_reg.h" 12e53ee4acSSai Krishna 13e53ee4acSSai Krishna /* RVUM block registers */ 14e53ee4acSSai Krishna #define RVU_PF_DISC (0x0) 15e53ee4acSSai Krishna #define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16) 16e53ee4acSSai Krishna #define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12) 17e53ee4acSSai Krishna 18e53ee4acSSai Krishna /* Mbox Registers */ 19e53ee4acSSai Krishna /* RVU AF BAR0 Mbox registers for AF => PFx */ 20e53ee4acSSai Krishna #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4) 21e53ee4acSSai Krishna #define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4) 22f326d5d8SSai Krishna #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3) 23f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6) 24f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6) 25f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0x2990 | (a) << 6) 26f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0x2998 | (a) << 6) 27f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF1_INT(a) (0x29A0 | (a) << 6) 28f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF1_INT_W1S(a) (0x29A8 | (a) << 6) 29f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF1_INT_ENA_W1S(a) (0x29B0 | (a) << 6) 30f326d5d8SSai Krishna #define RVU_MBOX_AF_PFAF1_INT_ENA_W1C(a) (0x29B8 | (a) << 6) 31f326d5d8SSai Krishna 32f326d5d8SSai Krishna /* RVU PF => AF mbox registers */ 33f326d5d8SSai Krishna #define RVU_MBOX_PF_PFAF_TRIGX(a) (0xC00 | (a) << 3) 34f326d5d8SSai Krishna #define RVU_MBOX_PF_INT (0xC20) 35f326d5d8SSai Krishna #define RVU_MBOX_PF_INT_W1S (0xC28) 36f326d5d8SSai Krishna #define RVU_MBOX_PF_INT_ENA_W1S (0xC30) 37f326d5d8SSai Krishna #define RVU_MBOX_PF_INT_ENA_W1C (0xC38) 38f326d5d8SSai Krishna 39e53ee4acSSai Krishna #define RVU_AF_BAR2_SEL (0x9000000) 40e53ee4acSSai Krishna #define RVU_AF_BAR2_PFID (0x16400) 41e53ee4acSSai Krishna #define NIX_CINTX_INT_W1S(a) (0xd30 | (a) << 12) 42e53ee4acSSai Krishna #define NIX_QINTX_CNT(a) (0xc00 | (a) << 12) 43e53ee4acSSai Krishna 44*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF_INT(a) (0x3000 | (a) << 6) 45*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF_INT_W1S(a) (0x3008 | (a) << 6) 46*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF_INT_ENA_W1S(a) (0x3010 | (a) << 6) 47*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0x3018 | (a) << 6) 48*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0x3018 | (a) << 6) 49*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF1_INT(a) (0x3020 | (a) << 6) 50*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF1_INT_W1S(a) (0x3028 | (a) << 6) 51*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF1_IN_ENA_W1S(a) (0x3030 | (a) << 6) 52*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFAF1_IN_ENA_W1C(a) (0x3038 | (a) << 6) 53*f8909d3dSSai Krishna 54*f8909d3dSSai Krishna #define RVU_MBOX_AF_AFVFX_TRIG(a, b) (0x10000 | (a) << 4 | (b) << 3) 55*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFX_ADDR(a) (0x20000 | (a) << 4) 56*f8909d3dSSai Krishna #define RVU_MBOX_AF_VFX_CFG(a) (0x28000 | (a) << 4) 57*f8909d3dSSai Krishna 58*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFX_PFVF_TRIGX(a) (0x2000 | (a) << 3) 59*f8909d3dSSai Krishna 60*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF_INTX(a) (0x1000 | (a) << 3) 61*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF_INT_W1SX(a) (0x1020 | (a) << 3) 62*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a) (0x1040 | (a) << 3) 63*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a) (0x1060 | (a) << 3) 64*f8909d3dSSai Krishna 65*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF1_INTX(a) (0x1080 | (a) << 3) 66*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF1_INT_W1SX(a) (0x10a0 | (a) << 3) 67*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a) (0x10c0 | (a) << 3) 68*f8909d3dSSai Krishna #define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a) (0x10e0 | (a) << 3) 69*f8909d3dSSai Krishna 70*f8909d3dSSai Krishna #define RVU_MBOX_PF_VF_ADDR (0xC40) 71*f8909d3dSSai Krishna #define RVU_MBOX_PF_LMTLINE_ADDR (0xC48) 72*f8909d3dSSai Krishna #define RVU_MBOX_PF_VF_CFG (0xC60) 73*f8909d3dSSai Krishna 74*f8909d3dSSai Krishna #define RVU_MBOX_VF_VFPF_TRIGX(a) (0x3000 | (a) << 3) 75*f8909d3dSSai Krishna #define RVU_MBOX_VF_INT (0x20) 76*f8909d3dSSai Krishna #define RVU_MBOX_VF_INT_W1S (0x28) 77*f8909d3dSSai Krishna #define RVU_MBOX_VF_INT_ENA_W1S (0x30) 78*f8909d3dSSai Krishna #define RVU_MBOX_VF_INT_ENA_W1C (0x38) 79*f8909d3dSSai Krishna 80*f8909d3dSSai Krishna #define RVU_MBOX_VF_VFAF_TRIGX(a) (0x2000 | (a) << 3) 81e53ee4acSSai Krishna #endif /* RVU_MBOX_REG_H */ 82