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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk104.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_privring_intr()
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/tools/testing/selftests/net/openvswitch/
H A Dopenvswitch.sh12 VERBOSE=0
13 TRACING=0
44 [ $VERBOSE = 0 ] || echo $*
52 return 0
57 local start=0
63 return 0
78 NO_BIN=0
189 return 0
195 if [ $? -ne 0 ]; then
199 return 0
[all...]
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux/arch/sh/include/asm/
H A Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/linux/include/linux/mfd/wm8350/
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
H A Daudio.h13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
/linux/include/linux/mfd/
H A Dwm8400-private.h16 #define WM8400_REGISTER_COUNT 0x55
28 #define WM8400_RESET_ID 0x00
29 #define WM8400_ID 0x01
30 #define WM8400_POWER_MANAGEMENT_1 0x02
31 #define WM8400_POWER_MANAGEMENT_2 0x03
32 #define WM8400_POWER_MANAGEMENT_3 0x04
33 #define WM8400_AUDIO_INTERFACE_1 0x05
34 #define WM8400_AUDIO_INTERFACE_2 0x06
35 #define WM8400_CLOCKING_1 0x07
36 #define WM8400_CLOCKING_2 0x08
[all …]
/linux/drivers/net/ethernet/cirrus/
H A Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dlocal_termination.sh44 00 00 3e 37 63 ff fe cf 17 0e 00 01 00 00 00 00 \
49 00 00 3e 37 63 ff fe cf 17 0e 00 01 00 00 02 00 \
52 01:80:c2:00:00:0e 00:00:de:ad:be:ef 88:f7 02 02 \
54 00 00 3e 37 63 ff fe cf 17 0e 00 01 00 06 05 7f \
59 00 48 0a 9a 40 00 01 11 cb 88 c0 00 02 01 e0 00 \
62 63 ff fe cf 17 0e 00 01 00 00 00 00 00 00 00 00 \
66 00 48 0a 9b 40 00 01 11 cb 87 c0 00 02 01 e0 00 \
69 63 ff fe cf 17 0e 00 01 00 00 02 00 00 00 66 83 \
70 c6 0f 1d 9a 61 87"
76 63 ff fe cf 17 0
[all...]
/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gen7_17_0_snapshot.h17 0x14000, 0x14034, 0x14036, 0x14036, 0x14040, 0x14042, 0x14044, 0x14045,
18 0x14047, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c, 0x14091, 0x14094,
19 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac, 0x140b1, 0x140b4,
20 0x140b9, 0x140bc, 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132,
21 0x14154, 0x1416b, 0x14340, 0x14341, 0x14344, 0x14344, 0x14346, 0x1437c,
22 0x143f0, 0x143f8, 0x143fa, 0x143fe, 0x14400, 0x14404, 0x14406, 0x1440a,
23 0x1440c, 0x14410, 0x14412, 0x14416, 0x14418, 0x1441c, 0x1441e, 0x14422,
24 0x14424, 0x14424, 0x14498, 0x144a0, 0x144a2, 0x144a6, 0x144a8, 0x144ac,
25 0x144ae, 0x144b2, 0x144b4, 0x144b8, 0x144ba, 0x144be, 0x144c0, 0x144c4,
26 0x144c6, 0x144ca, 0x144cc, 0x144cc, 0x14540, 0x14548, 0x1454a, 0x1454e,
[all …]
H A Dadreno_gen7_9_0_snapshot.h121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, PIPE_BR, A7XX_USPTP },
122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, PIPE_BR, A7XX_USPTP },
123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, PIPE_BR, A7XX_USPTP },
124 { A7XX_SP_INST_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
125 { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
126 { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
127 { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
128 { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
129 { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
130 { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, PIPE_BR, A7XX_USPTP },
[all …]
/linux/drivers/tty/serial/
H A Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-gateway-7001.dts18 memory@0 {
21 reg = <0x00000000 0x2000000>;
36 flash@0,0 {
42 reg = <0 0x00000000 0x800000>;
49 /* Eraseblock at 0x7e0000 */
50 fis-index-block = <0x3f>;
64 interrupt-map-mask = <0xf800 0 0 7>;
67 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
68 <0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */
69 <0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */
[all …]
H A Dintel-ixp42x-adi-coyote.dts19 memory@0 {
22 reg = <0x00000000 0x01000000>;
38 flash@0,0 {
42 * 32 MB of Flash in 128 0x20000 sized blocks
45 reg = <0 0x00000000 0x2000000>;
53 fis-index-block = <0x1ff>;
67 interrupt-map-mask = <0xf800 0 0 7>;
70 <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
71 <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
72 <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
[all …]
H A Dintel-ixp42x-netgear-wg302v1.dts19 memory@0 {
22 reg = <0x00000000 0x02000000>;
67 flash@0,0 {
71 * 8 MB of Flash in 64 0x20000 sized blocks
74 reg = <0 0x00000000 0x800000>;
81 fis-index-block = <0x3f>;
95 interrupt-map-mask = <0xf800 0 0 7>;
98 <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
99 <0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */
100 <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
[all …]
H A Dintel-ixp4xx-reference-design.dtsi9 memory@0 {
15 reg = <0x00000000 0x4000000>;
32 #size-cells = <0>;
40 reg = <0x50>;
50 nand-controller@3,0 {
62 intel,ixp4xx-eb-t1 = <0>;
63 intel,ixp4xx-eb-t2 = <0>;
65 intel,ixp4xx-eb-t4 = <0>;
66 intel,ixp4xx-eb-t5 = <0>;
67 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
[all …]
H A Dintel-ixp42x-linksys-nslu2.dts17 memory@0 {
20 reg = <0x00000000 0x2000000>;
36 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
79 #size-cells = <0>;
83 reg = <0x6f>;
101 pwms = <&gpio_pwm 0 1 0>;
108 flash@0,0 {
114 * 8 MB of Flash in 0x20000 byte blocks
117 reg = <0 0x00000000 0x800000>;
121 /* Eraseblock at 0x7e0000 */
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dintel,ixp4xx-pci.yaml54 - const: 0xf800
55 - const: 0
56 - const: 0
73 reg = <0xc0000000 0x1000>;
77 bus-range = <0x00 0xff>;
80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
86 interrupt-map-mask = <0xf800 0 0 7>;
88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
[all …]
/linux/include/dt-bindings/pinctrl/
H A Domap.h13 #define MUX_MODE0 0
38 #define PIN_OUTPUT 0
46 #define PIN_OFF_NONE 0
57 #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
59 #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
60 #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
61 #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
62 #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
63 #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
64 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
[all …]
/linux/include/linux/mfd/wm831x/
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/linux/drivers/net/ethernet/dec/tulip/
H A Deeprom.c29 {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
30 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
31 {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
32 0x0000, 0x009E, /* 10baseT */
33 0x0004, 0x009E, /* 10baseT-FD */
34 0x0903, 0x006D, /* 100baseTx */
35 0x0905, 0x006D, /* 100baseTx-FD */ }},
36 {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
37 0x0107, 0x8021, /* 100baseFx */
38 0x0108, 0x8021, /* 100baseFx-FD */
[all …]
/linux/include/sound/ac97/
H A Dregs.h13 #define AC97_RESET 0x00 /* Reset */
14 #define AC97_MASTER 0x02 /* Master Volume */
15 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
16 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
17 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
18 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */
19 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
20 #define AC97_MIC 0x0e /* MIC Volume */
21 #define AC97_LINE 0x10 /* Line In Volume */
22 #define AC97_CD 0x12 /* CD Volume */
[all …]

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