1*724ba675SRob Herring// SPDX-License-Identifier: ISC 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree file for ADI Engineering Coyote platform. 4*724ba675SRob Herring * Derived from boardfiles written by MontaVista software. 5*724ba675SRob Herring * Ethernet set-up from OpenWrt. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring/dts-v1/; 9*724ba675SRob Herring 10*724ba675SRob Herring#include "intel-ixp42x.dtsi" 11*724ba675SRob Herring#include <dt-bindings/input/input.h> 12*724ba675SRob Herring 13*724ba675SRob Herring/ { 14*724ba675SRob Herring model = "ADI Engineering Coyote reference design"; 15*724ba675SRob Herring compatible = "adieng,coyote", "intel,ixp42x"; 16*724ba675SRob Herring #address-cells = <1>; 17*724ba675SRob Herring #size-cells = <1>; 18*724ba675SRob Herring 19*724ba675SRob Herring memory@0 { 20*724ba675SRob Herring /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */ 21*724ba675SRob Herring device_type = "memory"; 22*724ba675SRob Herring reg = <0x00000000 0x01000000>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring 25*724ba675SRob Herring chosen { 26*724ba675SRob Herring bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; 27*724ba675SRob Herring stdout-path = "uart1:115200n8"; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring aliases { 31*724ba675SRob Herring /* These are switched around */ 32*724ba675SRob Herring serial0 = &uart1; 33*724ba675SRob Herring serial1 = &uart0; 34*724ba675SRob Herring }; 35*724ba675SRob Herring 36*724ba675SRob Herring soc { 37*724ba675SRob Herring bus@c4000000 { 38*724ba675SRob Herring flash@0,0 { 39*724ba675SRob Herring compatible = "intel,ixp4xx-flash", "cfi-flash"; 40*724ba675SRob Herring bank-width = <2>; 41*724ba675SRob Herring /* 42*724ba675SRob Herring * 32 MB of Flash in 128 0x20000 sized blocks 43*724ba675SRob Herring * mapped in at CS0 and CS1 44*724ba675SRob Herring */ 45*724ba675SRob Herring reg = <0 0x00000000 0x2000000>; 46*724ba675SRob Herring 47*724ba675SRob Herring /* Configure expansion bus to allow writes */ 48*724ba675SRob Herring intel,ixp4xx-eb-write-enable = <1>; 49*724ba675SRob Herring 50*724ba675SRob Herring partitions { 51*724ba675SRob Herring compatible = "redboot-fis"; 52*724ba675SRob Herring /* CHECKME: guess this is Redboot FIS */ 53*724ba675SRob Herring fis-index-block = <0x1ff>; 54*724ba675SRob Herring }; 55*724ba675SRob Herring }; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring pci@c0000000 { 59*724ba675SRob Herring status = "okay"; 60*724ba675SRob Herring 61*724ba675SRob Herring /* 62*724ba675SRob Herring * Taken from Coyote PCI boardfile. 63*724ba675SRob Herring * We have slots (IDSEL) 1 and 2 with one assigned IRQ 64*724ba675SRob Herring * each handling all IRQs. 65*724ba675SRob Herring */ 66*724ba675SRob Herring #interrupt-cells = <1>; 67*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 7>; 68*724ba675SRob Herring interrupt-map = 69*724ba675SRob Herring /* IDSEL 1 */ 70*724ba675SRob Herring <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */ 71*724ba675SRob Herring <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */ 72*724ba675SRob Herring <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */ 73*724ba675SRob Herring <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */ 74*724ba675SRob Herring /* IDSEL 2 */ 75*724ba675SRob Herring <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */ 76*724ba675SRob Herring <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */ 77*724ba675SRob Herring <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ 78*724ba675SRob Herring <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */ 79*724ba675SRob Herring }; 80*724ba675SRob Herring 81*724ba675SRob Herring /* EthB */ 82*724ba675SRob Herring ethernet@c8009000 { 83*724ba675SRob Herring status = "okay"; 84*724ba675SRob Herring queue-rx = <&qmgr 3>; 85*724ba675SRob Herring queue-txready = <&qmgr 20>; 86*724ba675SRob Herring phy-mode = "rgmii"; 87*724ba675SRob Herring phy-handle = <&phy5>; 88*724ba675SRob Herring 89*724ba675SRob Herring mdio { 90*724ba675SRob Herring #address-cells = <1>; 91*724ba675SRob Herring #size-cells = <0>; 92*724ba675SRob Herring 93*724ba675SRob Herring phy4: ethernet-phy@4 { 94*724ba675SRob Herring reg = <4>; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring phy5: ethernet-phy@5 { 98*724ba675SRob Herring reg = <5>; 99*724ba675SRob Herring }; 100*724ba675SRob Herring }; 101*724ba675SRob Herring }; 102*724ba675SRob Herring 103*724ba675SRob Herring /* EthC */ 104*724ba675SRob Herring ethernet@c800a000 { 105*724ba675SRob Herring status = "okay"; 106*724ba675SRob Herring queue-rx = <&qmgr 4>; 107*724ba675SRob Herring queue-txready = <&qmgr 21>; 108*724ba675SRob Herring phy-mode = "rgmii"; 109*724ba675SRob Herring phy-handle = <&phy4>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring }; 112*724ba675SRob Herring}; 113