1*724ba675SRob Herring// SPDX-License-Identifier: ISC 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree include file for Intel reference designs for the 4*724ba675SRob Herring * XScale Network Processors in the IXP 4xx series. Common device 5*724ba675SRob Herring * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring memory@0 { 10*724ba675SRob Herring /* 11*724ba675SRob Herring * The board supports up to 256 MB of memory. Here we put in 12*724ba675SRob Herring * 64 MB and this may be modified by the boot loader. 13*724ba675SRob Herring */ 14*724ba675SRob Herring device_type = "memory"; 15*724ba675SRob Herring reg = <0x00000000 0x4000000>; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring chosen { 19*724ba675SRob Herring bootargs = "console=ttyS0,115200n8"; 20*724ba675SRob Herring stdout-path = "uart0:115200n8"; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring aliases { 24*724ba675SRob Herring serial0 = &uart0; 25*724ba675SRob Herring }; 26*724ba675SRob Herring 27*724ba675SRob Herring i2c { 28*724ba675SRob Herring compatible = "i2c-gpio"; 29*724ba675SRob Herring sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 30*724ba675SRob Herring scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 31*724ba675SRob Herring #address-cells = <1>; 32*724ba675SRob Herring #size-cells = <0>; 33*724ba675SRob Herring 34*724ba675SRob Herring eeprom@50 { 35*724ba675SRob Herring /* 36*724ba675SRob Herring * Philips PCF8582C-2T/03 512byte I2C EEPROM 37*724ba675SRob Herring * should behave like an Atmel 24c04. 38*724ba675SRob Herring */ 39*724ba675SRob Herring compatible = "atmel,24c04"; 40*724ba675SRob Herring reg = <0x50>; 41*724ba675SRob Herring pagesize = <16>; 42*724ba675SRob Herring size = <512>; 43*724ba675SRob Herring read-only; 44*724ba675SRob Herring }; 45*724ba675SRob Herring }; 46*724ba675SRob Herring 47*724ba675SRob Herring soc { 48*724ba675SRob Herring bus@c4000000 { 49*724ba675SRob Herring /* Flash memory defined per-variant */ 50*724ba675SRob Herring nand-controller@3,0 { 51*724ba675SRob Herring /* Some designs have a NAND on CS3 enable it here if present */ 52*724ba675SRob Herring status = "disabled"; 53*724ba675SRob Herring 54*724ba675SRob Herring /* 55*724ba675SRob Herring * gen_nand needs to be extended and documented to get 56*724ba675SRob Herring * command byte = 1 and address byte = 2 from the device 57*724ba675SRob Herring * tree. 58*724ba675SRob Herring */ 59*724ba675SRob Herring compatible = "gen_nand"; 60*724ba675SRob Herring 61*724ba675SRob Herring /* Expansion bus set-up */ 62*724ba675SRob Herring intel,ixp4xx-eb-t1 = <0>; 63*724ba675SRob Herring intel,ixp4xx-eb-t2 = <0>; 64*724ba675SRob Herring intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase 65*724ba675SRob Herring intel,ixp4xx-eb-t4 = <0>; 66*724ba675SRob Herring intel,ixp4xx-eb-t5 = <0>; 67*724ba675SRob Herring intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type 68*724ba675SRob Herring intel,ixp4xx-eb-byte-access-on-halfword = <0>; 69*724ba675SRob Herring intel,ixp4xx-eb-mux-address-and-data = <0>; 70*724ba675SRob Herring intel,ixp4xx-eb-ahb-split-transfers = <0>; 71*724ba675SRob Herring intel,ixp4xx-eb-write-enable = <1>; 72*724ba675SRob Herring intel,ixp4xx-eb-byte-access = <1>; 73*724ba675SRob Herring 74*724ba675SRob Herring /* 512 bytes memory window */ 75*724ba675SRob Herring reg = <3 0x00000000 0x200>; 76*724ba675SRob Herring nand-on-flash-bbt; 77*724ba675SRob Herring nand-ecc-mode = "soft_bch"; 78*724ba675SRob Herring nand-ecc-step-size = <512>; 79*724ba675SRob Herring nand-ecc-strength = <4>; 80*724ba675SRob Herring nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ 81*724ba675SRob Herring 82*724ba675SRob Herring label = "ixp400 NAND"; 83*724ba675SRob Herring 84*724ba675SRob Herring partitions { 85*724ba675SRob Herring compatible = "fixed-partitions"; 86*724ba675SRob Herring #address-cells = <1>; 87*724ba675SRob Herring #size-cells = <1>; 88*724ba675SRob Herring 89*724ba675SRob Herring fs@0 { 90*724ba675SRob Herring label = "ixp400 NAND FS 0"; 91*724ba675SRob Herring reg = <0x0 0x800000>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring fs@800000 { 94*724ba675SRob Herring label = "ixp400 NAND FS 1"; 95*724ba675SRob Herring reg = <0x800000 0x0>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring }; 98*724ba675SRob Herring }; 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring pci@c0000000 { 102*724ba675SRob Herring status = "okay"; 103*724ba675SRob Herring 104*724ba675SRob Herring /* 105*724ba675SRob Herring * Taken from IXDP425 PCI boardfile. 106*724ba675SRob Herring * PCI slots on the BIXMB425BD base card. 107*724ba675SRob Herring * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. 108*724ba675SRob Herring */ 109*724ba675SRob Herring #interrupt-cells = <1>; 110*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 7>; 111*724ba675SRob Herring interrupt-map = 112*724ba675SRob Herring /* IDSEL 1 */ 113*724ba675SRob Herring <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ 114*724ba675SRob Herring <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ 115*724ba675SRob Herring <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ 116*724ba675SRob Herring <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ 117*724ba675SRob Herring /* IDSEL 2 */ 118*724ba675SRob Herring <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ 119*724ba675SRob Herring <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ 120*724ba675SRob Herring <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ 121*724ba675SRob Herring <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ 122*724ba675SRob Herring /* IDSEL 3 */ 123*724ba675SRob Herring <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ 124*724ba675SRob Herring <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ 125*724ba675SRob Herring <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ 126*724ba675SRob Herring <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ 127*724ba675SRob Herring /* IDSEL 4 */ 128*724ba675SRob Herring <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ 129*724ba675SRob Herring <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ 130*724ba675SRob Herring <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ 131*724ba675SRob Herring <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ 132*724ba675SRob Herring }; 133*724ba675SRob Herring }; 134*724ba675SRob Herring}; 135