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/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8812a.c21 s8 rx_pwr_all = 0; in rtw8812a_cck_rx_pwr()
48 case 0: in rtw8812a_cck_rx_pwr()
85 cont_tx = rtw_read32_mask(rtwdev, REG_SINGLE_TONE_CONT_TX, 0x70000); in rtw8812a_do_lck()
90 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); in rtw8812a_do_lck()
94 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000, 1); in rtw8812a_do_lck()
98 for (i = 0; i < 5; i++) { in rtw8812a_do_lck()
99 if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, 0x08000) != 1) in rtw8812a_do_lck()
110 rtw_write_rf(rtwdev, RF_PATH_A, RF_LCK, BIT(14), 0); in rtw8812a_do_lck()
113 rtw_write8(rtwdev, REG_TXPAUSE, 0); in rtw8812a_do_lck()
124 /* [31] = 0 --> Page C */ in rtw8812a_iqk_backup_rf()
[all …]
H A Drtw8821a.c21 static const s8 lna_gain_table[] = {15, -1, -17, 0, -30, -38}; in rtw8821a_cck_rx_pwr()
22 s8 rx_pwr_all = 0; in rtw8821a_cck_rx_pwr()
30 case 0: in rtw8821a_cck_rx_pwr()
62 /* [31] = 0 --> Page C */ in rtw8821a_iqk_backup_rf()
63 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw8821a_iqk_backup_rf()
66 for (i = 0; i < rf_num; i++) in rtw8821a_iqk_backup_rf()
77 /* [31] = 0 --> Page C */ in rtw8821a_iqk_restore_rf()
78 rtw_write32_mask(rtwdev, REG_CCASEL, BIT(31), 0x0); in rtw8821a_iqk_restore_rf()
80 for (i = 0; i < rf_reg_num; i++) in rtw8821a_iqk_restore_rf()
90 /* [31] = 0 --> Page C */ in rtw8821a_iqk_restore_afe()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dphy.h21 #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
22 #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
24 #define AR_PHY_BASE 0x9800
27 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
29 #define AR_PHY_TX_GAIN_CLC 0x0000001E
31 #define AR_PHY_TX_GAIN 0x0007F000
34 #define AR_PHY_CLC_TBL1 0xa35c
35 #define AR_PHY_CLC_I0 0x07ff0000
37 #define AR_PHY_CLC_Q0 0x0000ffd0
40 #define ANTSWAP_AB 0x0001
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h6 #define MCDE_IMSCPP 0x00000104
7 #define MCDE_RISPP 0x00000114
8 #define MCDE_MISPP 0x00000124
9 #define MCDE_SISPP 0x00000134
11 #define MCDE_PP_VCMPA BIT(0)
21 #define MCDE_IMSCOVL 0x00000108
22 #define MCDE_RISOVL 0x00000118
23 #define MCDE_MISOVL 0x00000128
24 #define MCDE_SISOVL 0x00000138
27 #define MCDE_IMSCCHNL 0x0000010C
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Damazon,al-alpine-v3-pcie.yaml57 reg = <0x0 0xfb600000 0x0 0x00100000
58 0x0 0xfd800000 0x0 0x00010000
59 0x0 0xfd810000 0x0 0x00001000>;
61 bus-range = <0 255>;
67 interrupt-map-mask = <0x00 0 0 7>;
68 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
69 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
/linux/drivers/usb/gadget/udc/
H A Damd5536udc.h37 #define UDC_SETCONFIG_DWORD0 0x00000900
38 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000
41 #define UDC_SETCONFIG_DWORD1 0x00000000
44 #define UDC_SETINTF_DWORD0 0x00000b00
45 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000
48 #define UDC_SETINTF_DWORD1 0x00000000
49 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff
50 #define UDC_SETINTF_DWORD1_INTF_OFS 0
53 #define UDC_MSCRES_DWORD0 0x0000ff21
54 #define UDC_MSCRES_DWORD1 0x00000000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv2a.c36 NVKM_MEM_TARGET_INST, 0x36b0, 16, true, in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv2a_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv2a_gr_chan_new()
49 for (i = 0x04d4; i <= 0x04e0; i += 4) in nv2a_gr_chan_new()
50 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
[all …]
H A Dnv25.c36 NVKM_MEM_TARGET_INST, 0x3724, 16, true, in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); in nv25_gr_chan_new()
[all …]
H A Dnv35.c36 NVKM_MEM_TARGET_INST, 0x577c, 16, true, in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); in nv35_gr_chan_new()
[all …]
H A Dnv34.c36 NVKM_MEM_TARGET_INST, 0x46dc, 16, true, in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0480, 0xffff0000); in nv34_gr_chan_new()
[all …]
H A Dnv30.c37 NVKM_MEM_TARGET_INST, 0x5f48, 16, true, in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
[all …]
H A Dctxnv40.c31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
35 * opcode 0x60000d is called before resuming normal operation.
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc9420.h21 /* Register set is duplicated for BE at an offset of 0x200 */
22 #define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
24 #define LAN9420_CPSR_ENDIAN_OFFSET (0)
27 #define PCI_VENDOR_ID_9420 (0x1055)
28 #define PCI_DEVICE_ID_9420 (0xE420)
30 #define LAN_REGISTER_EXTENT (0x400)
33 #define SMSC9420_EEPROM_MAGIC (0x9420)
40 #define BUS_MODE (0x00)
41 #define BUS_MODE_SWR_ (BIT(0))
50 #define TX_POLL_DEMAND (0x04)
[all …]
/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-p2m.c35 if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03)) in solo_p2m_dma()
61 unsigned int config = 0; in solo_p2m_dma_desc()
62 int ret = 0; in solo_p2m_dma_desc()
63 unsigned int p2m_id = 0; in solo_p2m_dma_desc()
65 /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */ in solo_p2m_dma_desc()
75 p2m_dev->error = 0; in solo_p2m_dma_desc()
79 p2m_dev->desc_count = p2m_dev->desc_idx = 0; in solo_p2m_dma_desc()
107 else if (time_left == 0) { in solo_p2m_dma_desc()
112 solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0); in solo_p2m_dma_desc()
114 /* Don't write here for the no_desc_mode case, because config is 0. in solo_p2m_dma_desc()
[all …]
/linux/drivers/message/fusion/lsi/
H A Dmpi_lan.h58 SGE_MPI_UNION SG_List[1]; /* 0Ch */
73 U16 Reserved3; /* 0Ch */
74 U16 IOCStatus; /* 0Eh */
92 U32 BucketCount; /* 0Ch */
108 U16 Reserved3; /* 0Ch */
109 U16 IOCStatus; /* 0Eh */
143 U16 Reserved3; /* 0Ch */
144 U16 IOCStatus; /* 0Eh */
154 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF)
155 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0)
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-conf-reg.h13 #define BOARD_CFG_STAT 0x0
14 #define TS_MODE_REG 0x4
15 #define TS1_CFG_REG 0x8
16 #define TS1_LENGTH_REG 0xc
17 #define TS2_CFG_REG 0x10
18 #define TS2_LENGTH_REG 0x14
19 #define EP_MODE_SET 0x18
20 #define CIR_PWR_PTN1 0x1c
21 #define CIR_PWR_PTN2 0x20
22 #define CIR_PWR_PTN3 0x24
[all …]
/linux/arch/mips/include/asm/sn/
H A Dioc3.h30 u8 iu_ier; /* DLAB == 0 */
34 u8 iu_rbr; /* read only, DLAB == 0 */
35 u8 iu_thr; /* write only, DLAB == 0 */
45 u8 fill[0x141]; /* starts at 0x141 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
69 struct ioc3_uartregs uartb; /* 0x20170 */
70 struct ioc3_uartregs uarta; /* 0x20178 */
[all …]
/linux/drivers/pci/hotplug/
H A Dshpchp_hpc.c25 #define SLOT_33MHZ 0x0000001f
26 #define SLOT_66MHZ_PCIX 0x00001f00
27 #define SLOT_100MHZ_PCIX 0x001f0000
28 #define SLOT_133MHZ_PCIX 0x1f000000
31 #define SLOT_66MHZ 0x0000001f
32 #define SLOT_66MHZ_PCIX_266 0x00000f00
33 #define SLOT_100MHZ_PCIX_266 0x0000f000
34 #define SLOT_133MHZ_PCIX_266 0x000f0000
35 #define SLOT_66MHZ_PCIX_533 0x00f00000
36 #define SLOT_100MHZ_PCIX_533 0x0f000000
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Drx_desc.h14 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
58 * 0. The PPDU start status will only be valid when this bit
67 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
228 * ring 0. Field is filled in by the RX_DMA.
244 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
257 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
258 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
259 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
261 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
269 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux/include/video/
H A Dmach64.h20 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21 #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23 #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
24 #define CRTC_H_SYNC_STRT 0x0004
25 #define CRTC2_H_SYNC_STRT 0x0004
26 #define CRTC_H_SYNC_DLY 0x0005
27 #define CRTC2_H_SYNC_DLY 0x0005
28 #define CRTC_H_SYNC_WID 0x0006
29 #define CRTC2_H_SYNC_WID 0x0006
[all …]

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