Lines Matching +full:0 +full:x07ff0000
25 #define SLOT_33MHZ 0x0000001f
26 #define SLOT_66MHZ_PCIX 0x00001f00
27 #define SLOT_100MHZ_PCIX 0x001f0000
28 #define SLOT_133MHZ_PCIX 0x1f000000
31 #define SLOT_66MHZ 0x0000001f
32 #define SLOT_66MHZ_PCIX_266 0x00000f00
33 #define SLOT_100MHZ_PCIX_266 0x0000f000
34 #define SLOT_133MHZ_PCIX_266 0x000f0000
35 #define SLOT_66MHZ_PCIX_533 0x00f00000
36 #define SLOT_100MHZ_PCIX_533 0x0f000000
37 #define SLOT_133MHZ_PCIX_533 0xf0000000
40 #define SLOT_NUM 0x0000001F
41 #define FIRST_DEV_NUM 0x00001F00
42 #define PSN 0x07FF0000
43 #define UPDOWN 0x20000000
44 #define MRLSENSOR 0x40000000
45 #define ATTN_BUTTON 0x80000000
50 #define CMD_INTR_PENDING (1 << 0)
56 #define GLOBAL_INTR_MASK (1 << 0)
62 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
69 #define SLOT_STATE_SHIFT (0)
70 #define SLOT_STATE_MASK (3 << 0)
115 #define SET_SLOT_PWR 0x01 /* Slot Operation */
116 #define SET_SLOT_ENABLE 0x02
117 #define SET_SLOT_DISABLE 0x03
118 #define SET_PWR_ON 0x04
119 #define SET_PWR_BLINK 0x08
120 #define SET_PWR_OFF 0x0c
121 #define SET_ATTN_ON 0x10
122 #define SET_ATTN_BLINK 0x20
123 #define SET_ATTN_OFF 0x30
124 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
125 #define SETA_PCI_66MHZ 0x41
126 #define SETA_PCIX_66MHZ 0x42
127 #define SETA_PCIX_100MHZ 0x43
128 #define SETA_PCIX_133MHZ 0x44
129 #define SETA_RESERVED1 0x45
130 #define SETA_RESERVED2 0x46
131 #define SETA_RESERVED3 0x47
132 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
133 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
134 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
135 #define SETB_PCI_66MHZ 0x51
136 #define SETB_PCIX_66MHZ_PM 0x52
137 #define SETB_PCIX_100MHZ_PM 0x53
138 #define SETB_PCIX_133MHZ_PM 0x54
139 #define SETB_PCIX_66MHZ_EM 0x55
140 #define SETB_PCIX_100MHZ_EM 0x56
141 #define SETB_PCIX_133MHZ_EM 0x57
142 #define SETB_PCIX_66MHZ_266 0x58
143 #define SETB_PCIX_100MHZ_266 0x59
144 #define SETB_PCIX_133MHZ_266 0x5a
145 #define SETB_PCIX_66MHZ_533 0x5b
146 #define SETB_PCIX_100MHZ_533 0x5c
147 #define SETB_PCIX_133MHZ_533 0x5d
148 #define SETB_RESERVED1 0x5e
149 #define SETB_RESERVED2 0x5f
154 #define SWITCH_OPEN 0x1
155 #define INVALID_CMD 0x2
156 #define INVALID_SPEED_MODE 0x4
161 #define DWORD_SELECT 0x2
162 #define DWORD_DATA 0x4
165 #define SLOT_EVENT_LATCH 0x2
166 #define SLOT_SERR_INT_MASK 0x3
217 shpc_isr(0, ctrl); in int_poll_timeout()
231 if ((sec <= 0) || (sec > 60)) in start_int_poll_timer()
241 return cmd_status & 0x1; in is_ctrl_busy()
246 * otherwise returns 0.
256 for (i = 0; i < 10; i++) { in shpc_poll_ctrl_busy()
262 return 0; in shpc_poll_ctrl_busy()
267 int retval = 0; in shpc_wait_cmd()
279 } else if (rc < 0) { in shpc_wait_cmd()
291 int retval = 0; in shpc_write_cmd()
304 temp_word = (t_slot << 8) | (cmd & 0xFF); in shpc_write_cmd()
307 /* To make sure the Controller Busy bit is 0 before we send out the in shpc_write_cmd()
321 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", in shpc_write_cmd()
332 int retval = 0; in shpchp_check_cmd_status()
333 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; in shpchp_check_cmd_status()
336 case 0: in shpchp_check_cmd_status()
337 retval = 0; in shpchp_check_cmd_status()
373 *status = 0; /* Off */ in shpchp_get_attention_status()
376 *status = 0xFF; /* Reserved */ in shpchp_get_attention_status()
380 return 0; in shpchp_get_attention_status()
397 *status = 0; /* Disabled */ in shpchp_get_power_status()
400 *status = 0xFF; /* Reserved */ in shpchp_get_power_status()
404 return 0; in shpchp_get_power_status()
413 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ in shpchp_get_latch_status()
415 return 0; in shpchp_get_latch_status()
424 *status = (state != 0x3) ? 1 : 0; in shpchp_get_adapter_status()
426 return 0; in shpchp_get_adapter_status()
435 return 0; in shpchp_get_prog_int()
440 int retval = 0; in shpchp_get_adapter_speed()
465 case 0x0: in shpchp_get_adapter_speed()
468 case 0x1: in shpchp_get_adapter_speed()
471 case 0x3: in shpchp_get_adapter_speed()
474 case 0x4: in shpchp_get_adapter_speed()
477 case 0x5: in shpchp_get_adapter_speed()
480 case 0x2: in shpchp_get_adapter_speed()
496 /* Note: Logic 0 => fault */ in shpchp_query_power_fault()
502 u8 slot_cmd = 0; in shpchp_set_attention_status()
505 case 0: in shpchp_set_attention_status()
545 for (i = 0; i < ctrl->num_slots; i++) { in shpchp_release_ctlr()
616 int retval = 0; in shpc_get_cur_bus_speed()
621 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); in shpc_get_cur_bus_speed()
629 case 0x0: in shpc_get_cur_bus_speed()
632 case 0x1: in shpc_get_cur_bus_speed()
635 case 0x2: in shpc_get_cur_bus_speed()
638 case 0x3: in shpc_get_cur_bus_speed()
641 case 0x4: in shpc_get_cur_bus_speed()
644 case 0x5: in shpc_get_cur_bus_speed()
647 case 0x6: in shpc_get_cur_bus_speed()
650 case 0x7: in shpc_get_cur_bus_speed()
653 case 0x8: in shpc_get_cur_bus_speed()
656 case 0x9: in shpc_get_cur_bus_speed()
659 case 0xa: in shpc_get_cur_bus_speed()
662 case 0xb: in shpc_get_cur_bus_speed()
665 case 0xc: in shpc_get_cur_bus_speed()
668 case 0xd: in shpc_get_cur_bus_speed()
740 retval = shpc_write_cmd(slot, 0, cmd); in shpchp_set_bus_speed_mode()
792 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { in shpc_isr()
830 int retval = 0; in shpc_get_max_bus_speed()
875 int rc = -1, num_slots = 0; in shpc_init()
886 /* amd shpc driver doesn't use Base Offset; assume 0 */ in shpc_init()
887 ctrl->mmio_base = pci_resource_start(pdev, 0); in shpc_init()
888 ctrl->mmio_size = pci_resource_len(pdev, 0); in shpc_init()
897 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); in shpc_init()
911 for (i = 0; i < 9 + num_slots; i++) { in shpc_init()
922 pci_resource_start(pdev, 0) + shpc_base_offset; in shpc_init()
923 ctrl->mmio_size = 0x24 + 0x4 * num_slots; in shpc_init()
978 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { in shpc_init()
992 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); in shpc_init()
1022 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { in shpc_init()
1041 return 0; in shpc_init()