Lines Matching +full:0 +full:x07ff0000
37 #define UDC_SETCONFIG_DWORD0 0x00000900
38 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000
41 #define UDC_SETCONFIG_DWORD1 0x00000000
44 #define UDC_SETINTF_DWORD0 0x00000b00
45 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000
48 #define UDC_SETINTF_DWORD1 0x00000000
49 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff
50 #define UDC_SETINTF_DWORD1_INTF_OFS 0
53 #define UDC_MSCRES_DWORD0 0x0000ff21
54 #define UDC_MSCRES_DWORD1 0x00000000
57 #define UDC_CSR_ADDR 0x500
61 #define UDC_CSR_NE_NUM_MASK 0x0000000f
62 #define UDC_CSR_NE_NUM_OFS 0
64 #define UDC_CSR_NE_DIR_MASK 0x00000010
67 #define UDC_CSR_NE_TYPE_MASK 0x00000060
70 #define UDC_CSR_NE_CFG_MASK 0x00000780
73 #define UDC_CSR_NE_INTF_MASK 0x00007800
76 #define UDC_CSR_NE_ALT_MASK 0x00078000
80 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
84 #define UDC_DEVCFG_ADDR 0x400
98 #define UDC_DEVCFG_SPD_MASK 0x3
99 #define UDC_DEVCFG_SPD_OFS 0
100 #define UDC_DEVCFG_SPD_HS 0x0
101 #define UDC_DEVCFG_SPD_FS 0x1
102 #define UDC_DEVCFG_SPD_LS 0x2
103 /*#define UDC_DEVCFG_SPD_FS 0x3*/
107 #define UDC_DEVCTL_ADDR 0x404
109 #define UDC_DEVCTL_THLEN_MASK 0xff000000
112 #define UDC_DEVCTL_BRLEN_MASK 0x00ff0000
127 #define UDC_DEVCTL_RES 0
131 #define UDC_DEVSTS_ADDR 0x408
133 #define UDC_DEVSTS_TS_MASK 0xfffc0000
140 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
143 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
147 #define UDC_DEVSTS_ALT_MASK 0x00000f00
150 #define UDC_DEVSTS_INTF_MASK 0x000000f0
153 #define UDC_DEVSTS_CFG_MASK 0x0000000f
154 #define UDC_DEVSTS_CFG_OFS 0
158 #define UDC_DEVINT_ADDR 0x40c
167 #define UDC_DEVINT_SC 0
170 #define UDC_DEVINT_MSK_ADDR 0x410
172 #define UDC_DEVINT_MSK 0x7f
175 #define UDC_EPINT_ADDR 0x414
177 #define UDC_EPINT_OUT_MASK 0xffff0000
179 #define UDC_EPINT_IN_MASK 0x0000ffff
180 #define UDC_EPINT_IN_OFS 0
182 #define UDC_EPINT_IN_EP0 0
191 #define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e
194 #define UDC_EPINT_MSK_ADDR 0x418
196 #define UDC_EPINT_OUT_MSK_MASK 0xffff0000
198 #define UDC_EPINT_IN_MSK_MASK 0x0000ffff
199 #define UDC_EPINT_IN_MSK_OFS 0
201 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
203 #define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe
205 #define UDC_DEV_MSK_DISABLE 0x7f
208 #define UDC_EPREGS_ADDR 0x0
209 #define UDC_EPIN_REGS_ADDR 0x0
210 #define UDC_EPOUT_REGS_ADDR 0x200
212 #define UDC_EPCTL_ADDR 0x0
219 #define UDC_EPCTL_ET_MASK 0x00000030
221 #define UDC_EPCTL_ET_CONTROL 0
229 #define UDC_EPCTL_S 0
232 #define UDC_EPSTS_ADDR 0x4
234 #define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800
242 #define UDC_EPSTS_OUT_MASK 0x00000030
245 #define UDC_EPSTS_OUT_DATA_CLEAR 0x10
247 #define UDC_EPSTS_OUT_SETUP_CLEAR 0x20
248 #define UDC_EPSTS_OUT_CLEAR 0x30
251 #define UDC_EPIN_BUFF_SIZE_ADDR 0x8
252 #define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8
254 #define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff
255 #define UDC_EPIN_BUFF_SIZE_OFS 0
272 #define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff
273 #define UDC_EPOUT_FRAME_NUMBER_OFS 0
276 #define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c
277 #define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c
279 #define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000
281 #define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff
282 #define UDC_EP_MAX_PKT_SIZE_OFS 0
297 #define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000
299 #define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000
301 #define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000
303 #define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000
305 #define UDC_DMA_STP_STS_RX_MASK 0x30000000
307 #define UDC_DMA_STP_STS_BS_MASK 0xc0000000
309 #define UDC_DMA_STP_STS_BS_HOST_READY 0
314 #define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff
315 #define UDC_DMA_IN_STS_TXBYTES_OFS 0
316 #define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000
317 #define UDC_DMA_IN_STS_FRAMENUM_OFS 0
319 #define UDC_DMA_IN_STS_TX_MASK 0x30000000
321 #define UDC_DMA_IN_STS_BS_MASK 0xc0000000
323 #define UDC_DMA_IN_STS_BS_HOST_READY 0
328 #define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff
329 #define UDC_DMA_OUT_STS_RXBYTES_OFS 0
330 #define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000
331 #define UDC_DMA_OUT_STS_FRAMENUM_OFS 0
333 #define UDC_DMA_OUT_STS_RX_MASK 0x30000000
335 #define UDC_DMA_OUT_STS_BS_MASK 0xc0000000
337 #define UDC_DMA_OUT_STS_BS_HOST_READY 0
347 #define DMA_DONT_USE (~(dma_addr_t) 0 )
350 #define UDC_EP_SUBPTR_ADDR 0x10
351 #define UDC_EP_DESPTR_ADDR 0x14
352 #define UDC_EP_WRITE_CONFIRM_ADDR 0x1c
365 #define UDC_EP0IN_IX 0
368 #define UDC_RXFIFO_ADDR 0x800
369 #define UDC_RXFIFO_SIZE 0x400
372 #define UDC_TXFIFO_ADDR 0xc00
373 #define UDC_TXFIFO_SIZE 0x600
383 #define UDC_BYTE_MASK 0xff
658 #define VDBG(udc , args...) do {} while (0)