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/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/linux/drivers/clk/imx/
H A Dclk-pllv2.c17 #define MXC_PLL_DP_CTL 0x00
18 #define MXC_PLL_DP_CONFIG 0x04
19 #define MXC_PLL_DP_OP 0x08
20 #define MXC_PLL_DP_MFD 0x0C
21 #define MXC_PLL_DP_MFN 0x10
22 #define MXC_PLL_DP_MFNMINUS 0x14
23 #define MXC_PLL_DP_MFNPLUS 0x18
24 #define MXC_PLL_DP_HFS_OP 0x1C
25 #define MXC_PLL_DP_HFS_MFD 0x20
26 #define MXC_PLL_DP_HFS_MFN 0x24
[all …]
/linux/arch/powerpc/sysdev/
H A Ddart.h11 #define DART_CNTL 0
14 #define DART_EXCP_U3 0x10
16 #define DART_TAGS_U3 0x1000
19 #define DART_BASE_U4 0x10
20 #define DART_SIZE_U4 0x20
21 #define DART_EXCP_U4 0x30
22 #define DART_TAGS_U4 0x1000
27 #define DART_CNTL_U3_BASE_MASK 0xfffff
29 #define DART_CNTL_U3_FLUSHTLB 0x400
30 #define DART_CNTL_U3_ENABLE 0x200
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_wrot.h10 #define VIDO_CTRL 0x000
11 #define VIDO_MAIN_BUF_SIZE 0x008
12 #define VIDO_SOFT_RST 0x010
13 #define VIDO_SOFT_RST_STAT 0x014
14 #define VIDO_CROP_OFST 0x020
15 #define VIDO_TAR_SIZE 0x024
16 #define VIDO_OFST_ADDR 0x02c
17 #define VIDO_STRIDE 0x030
18 #define VIDO_OFST_ADDR_C 0x038
19 #define VIDO_STRIDE_C 0x03c
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux/drivers/scsi/
H A Dgvp11.c33 #define TO_DMA_MASK(m) (~((unsigned long long)m & 0xffffffff))
51 static int gvp11_xfer_mask = 0;
64 static int scsi_alloc_out_of_range = 0; in dma_setup()
83 wh->dma_bounce_len = (scsi_pointer->this_residual + 511) & ~0x1ff; in dma_setup()
98 wh->dma_bounce_len = 0; in dma_setup()
144 wh->dma_bounce_len = 0; in dma_setup()
175 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
183 return 0; in dma_setup()
216 wh->dma_bounce_len = 0; in dma_stop()
262 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
H A Dcik.c82 .max_level = 0,
143 return 0; in cik_query_video_codecs()
205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
245 0xc200, 0xe0ffffff, 0xe0000000
250 0x31dc, 0xffffffff, 0x00000800,
251 0x31dd, 0xffffffff, 0x00000800,
252 0x31e6, 0xffffffff, 0x00007fbf,
253 0x31e7, 0xffffffff, 0x00007faf
258 0xcd5, 0x00000333, 0x00000333,
[all …]
/linux/arch/powerpc/include/asm/
H A Ddbell.h19 #define PPC_DBELL_MSG_BRDCAST (0x04000000)
20 #define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
21 #define PPC_DBELL_TYPE_MASK PPC_DBELL_TYPE(0xf)
23 #define PPC_DBELL_PIR_MASK 0x3fff
25 PPC_DBELL = 0, /* doorbell */
39 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGSND(%1), PPC_MSGSNDP(%1), %0) in _ppc_msgsnd()
53 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGSYNC " ; lwsync", "", %0) in ppc_msgsync()
59 __asm__ __volatile__ (ASM_FTR_IFSET(PPC_MSGCLR(%1), PPC_MSGCLRP(%1), %0) in _ppc_msgclr()
76 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); in _ppc_msgsnd()
97 (tag & 0x07ffffff); in ppc_msgsnd()
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dsc.h13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]
/linux/drivers/char/xilinx_hwicap/
H A Dxilinx_hwicap.h43 u32 write_buffer_in_use; /* Always in [0,3] */
45 u32 read_buffer_in_use; /* Always in [0,3] */
65 * Return 0 if successful.
70 * Return 0 if successful.
75 * D8 - 0 = configuration error
78 * D5 - 0 = abort in progress
101 #define XHI_PAD_FRAMES 0x1
104 #define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
105 #define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
106 #define XHI_TYPE_MASK 0x7
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/drivers/usb/musb/
H A Dtusb6010.h12 /* VLYNQ control register. 32-bit at offset 0x000 */
13 #define TUSB_VLYNQ_CTRL 0x004
15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
16 #define TUSB_BASE_OFFSET 0x400
18 /* FIFO registers 32-bit at offset 0x600 */
19 #define TUSB_FIFO_BASE 0x600
21 /* Device System & Control registers. 32-bit at offset 0x800 */
22 #define TUSB_SYS_REG_BASE 0x800
24 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
28 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmnv44.c30 u32 pteo = (ptei << 2) & ~0x0000000f; in nv44_vmm_pgt_fill()
33 tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0); in nv44_vmm_pgt_fill()
34 tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4); in nv44_vmm_pgt_fill()
35 tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8); in nv44_vmm_pgt_fill()
36 tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc); in nv44_vmm_pgt_fill()
40 switch (ptei++ & 0x3) { in nv44_vmm_pgt_fill()
41 case 0: in nv44_vmm_pgt_fill()
42 tmp[0] &= ~0x07ffffff; in nv44_vmm_pgt_fill()
43 tmp[0] |= addr; in nv44_vmm_pgt_fill()
46 tmp[0] &= ~0xf8000000; in nv44_vmm_pgt_fill()
[all …]
/linux/drivers/message/fusion/lsi/
H A Dmpi_lan.h58 SGE_MPI_UNION SG_List[1]; /* 0Ch */
73 U16 Reserved3; /* 0Ch */
74 U16 IOCStatus; /* 0Eh */
92 U32 BucketCount; /* 0Ch */
108 U16 Reserved3; /* 0Ch */
109 U16 IOCStatus; /* 0Eh */
143 U16 Reserved3; /* 0Ch */
144 U16 IOCStatus; /* 0Eh */
154 #define LAN_REPLY_PACKET_LENGTH_MASK (0x0000FFFF)
155 #define LAN_REPLY_PACKET_LENGTH_SHIFT (0)
[all …]
/linux/arch/parisc/math-emu/
H A Ddecode_exc.c41 #define Fpustatus_register Fpu_register[0]
45 #define NOTRAP 0
58 #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0
81 if ((Dallp2(dbl_valuep2)--) == 0) Dallp1(dbl_valuep1)--
86 aflags=(Fpu_register[0])>>27; /* assumes zero fill. 32 bit */ \
87 Fpu_register[0] |= bflags; \
104 * need to restore Fpu_register[0] in decode_fpu()
107 bflags=(Fpu_register[0] & 0xf8000000); in decode_fpu()
108 Fpu_register[0] &= 0x07ffffff; in decode_fpu()
139 * codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds in decode_fpu()
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1xxx_dbdma.h50 #define DDMA_CONFIG_AL (1 << 0)
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
75 #define DDMA_CFG_EN (1 << 0) /* Channel enable */
82 #define DDMA_IRQ_IN (1 << 0)
86 #define DDMA_STAT_H (1 << 0) /* Channel Halted */
112 #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/linux/arch/alpha/include/asm/
H A Dcore_mcpcia.h58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x058
[all …]
H A Dcore_cia.h48 * 00 00 Byte 1110 0x000
49 * 01 00 Byte 1101 0x020
50 * 10 00 Byte 1011 0x040
51 * 11 00 Byte 0111 0x060
53 * 00 01 Word 1100 0x008
54 * 01 01 Word 1001 0x028 <= Not supported in this code.
55 * 10 01 Word 0011 0x048
57 * 00 10 Tribyte 1000 0x010
58 * 01 10 Tribyte 0001 0x030
60 * 10 11 Longword 0000 0x058
[all …]

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