Lines Matching +full:0 +full:x07ffffff
17 #define MXC_PLL_DP_CTL 0x00
18 #define MXC_PLL_DP_CONFIG 0x04
19 #define MXC_PLL_DP_OP 0x08
20 #define MXC_PLL_DP_MFD 0x0C
21 #define MXC_PLL_DP_MFN 0x10
22 #define MXC_PLL_DP_MFNMINUS 0x14
23 #define MXC_PLL_DP_MFNPLUS 0x18
24 #define MXC_PLL_DP_HFS_OP 0x1C
25 #define MXC_PLL_DP_HFS_MFD 0x20
26 #define MXC_PLL_DP_HFS_MFN 0x24
27 #define MXC_PLL_DP_MFN_TOGC 0x28
28 #define MXC_PLL_DP_DESTAT 0x2c
31 #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
32 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
34 #define MXC_PLL_DP_CTL_ADE 0x800
35 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
38 #define MXC_PLL_DP_CTL_HFSM 0x80
39 #define MXC_PLL_DP_CTL_PRE 0x40
40 #define MXC_PLL_DP_CTL_UPEN 0x20
41 #define MXC_PLL_DP_CTL_RST 0x10
42 #define MXC_PLL_DP_CTL_RCP 0x8
43 #define MXC_PLL_DP_CTL_PLM 0x4
44 #define MXC_PLL_DP_CTL_BRM0 0x2
45 #define MXC_PLL_DP_CTL_LRF 0x1
47 #define MXC_PLL_DP_CONFIG_BIST 0x8
48 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
49 #define MXC_PLL_DP_CONFIG_AREN 0x2
50 #define MXC_PLL_DP_CONFIG_LDREQ 0x1
53 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
54 #define MXC_PLL_DP_OP_PDF_OFFSET 0
55 #define MXC_PLL_DP_OP_PDF_MASK 0xF
57 #define MXC_PLL_DP_MFD_OFFSET 0
58 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
60 #define MXC_PLL_DP_MFN_OFFSET 0x0
61 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
65 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
66 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
69 #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
95 if (dbl != 0) in __clk_pllv2_recalc_rate()
101 if (mfn < 0) in __clk_pllv2_recalc_rate()
152 return 0; in __clk_pllv2_set_rate()
172 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); in clk_pllv2_set_rate()
178 return 0; in clk_pllv2_set_rate()
200 int i = 0; in clk_pllv2_prepare()
220 return 0; in clk_pllv2_prepare()
258 init.flags = 0; in imx_clk_hw_pllv2()