1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2024b246eSLinus Torvalds #ifndef __ALPHA_CIA__H__
3024b246eSLinus Torvalds #define __ALPHA_CIA__H__
4024b246eSLinus Torvalds
5024b246eSLinus Torvalds /* Define to experiment with fitting everything into one 512MB HAE window. */
6024b246eSLinus Torvalds #define CIA_ONE_HAE_WINDOW 1
7024b246eSLinus Torvalds
8024b246eSLinus Torvalds #include <linux/types.h>
9024b246eSLinus Torvalds #include <asm/compiler.h>
10024b246eSLinus Torvalds
11024b246eSLinus Torvalds /*
12024b246eSLinus Torvalds * CIA is the internal name for the 21171 chipset which provides
13024b246eSLinus Torvalds * memory controller and PCI access for the 21164 chip based systems.
14024b246eSLinus Torvalds * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
15024b246eSLinus Torvalds *
16024b246eSLinus Torvalds * The lineage is a bit confused, since the 21174 was reportedly started
17024b246eSLinus Torvalds * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
18024b246eSLinus Torvalds * in 21171 Pass 2 and 21172, but it also contains additional features.
19024b246eSLinus Torvalds *
20024b246eSLinus Torvalds * This file is based on:
21024b246eSLinus Torvalds *
22024b246eSLinus Torvalds * DECchip 21171 Core Logic Chipset
23024b246eSLinus Torvalds * Technical Reference Manual
24024b246eSLinus Torvalds *
25024b246eSLinus Torvalds * EC-QE18B-TE
26024b246eSLinus Torvalds *
27024b246eSLinus Torvalds * david.rusling@reo.mts.dec.com Initial Version.
28024b246eSLinus Torvalds *
29024b246eSLinus Torvalds */
30024b246eSLinus Torvalds
31024b246eSLinus Torvalds /*
32024b246eSLinus Torvalds * CIA ADDRESS BIT DEFINITIONS
33024b246eSLinus Torvalds *
34024b246eSLinus Torvalds * 3333 3333 3322 2222 2222 1111 1111 11
35024b246eSLinus Torvalds * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
36024b246eSLinus Torvalds * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
37024b246eSLinus Torvalds * 1 000
38024b246eSLinus Torvalds * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
39024b246eSLinus Torvalds * | |\|
40024b246eSLinus Torvalds * | Byte Enable --+ |
41024b246eSLinus Torvalds * | Transfer Length --+
42024b246eSLinus Torvalds * +-- IO space, not cached
43024b246eSLinus Torvalds *
44024b246eSLinus Torvalds * Byte Transfer
45024b246eSLinus Torvalds * Enable Length Transfer Byte Address
46024b246eSLinus Torvalds * adr<6:5> adr<4:3> Length Enable Adder
47024b246eSLinus Torvalds * ---------------------------------------------
48024b246eSLinus Torvalds * 00 00 Byte 1110 0x000
49024b246eSLinus Torvalds * 01 00 Byte 1101 0x020
50024b246eSLinus Torvalds * 10 00 Byte 1011 0x040
51024b246eSLinus Torvalds * 11 00 Byte 0111 0x060
52024b246eSLinus Torvalds *
53024b246eSLinus Torvalds * 00 01 Word 1100 0x008
54024b246eSLinus Torvalds * 01 01 Word 1001 0x028 <= Not supported in this code.
55024b246eSLinus Torvalds * 10 01 Word 0011 0x048
56024b246eSLinus Torvalds *
57024b246eSLinus Torvalds * 00 10 Tribyte 1000 0x010
58024b246eSLinus Torvalds * 01 10 Tribyte 0001 0x030
59024b246eSLinus Torvalds *
60024b246eSLinus Torvalds * 10 11 Longword 0000 0x058
61024b246eSLinus Torvalds *
62024b246eSLinus Torvalds * Note that byte enables are asserted low.
63024b246eSLinus Torvalds *
64024b246eSLinus Torvalds */
65024b246eSLinus Torvalds
66024b246eSLinus Torvalds #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
67024b246eSLinus Torvalds #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
68024b246eSLinus Torvalds #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
69024b246eSLinus Torvalds
70024b246eSLinus Torvalds /*
71024b246eSLinus Torvalds * 21171-CA Control and Status Registers
72024b246eSLinus Torvalds */
73024b246eSLinus Torvalds #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
74024b246eSLinus Torvalds # define CIA_REV_MASK 0xff
75024b246eSLinus Torvalds #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76024b246eSLinus Torvalds #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
77024b246eSLinus Torvalds # define CIA_CTRL_PCI_EN (1 << 0)
78024b246eSLinus Torvalds # define CIA_CTRL_PCI_LOCK_EN (1 << 1)
79024b246eSLinus Torvalds # define CIA_CTRL_PCI_LOOP_EN (1 << 2)
80024b246eSLinus Torvalds # define CIA_CTRL_FST_BB_EN (1 << 3)
81024b246eSLinus Torvalds # define CIA_CTRL_PCI_MST_EN (1 << 4)
82024b246eSLinus Torvalds # define CIA_CTRL_PCI_MEM_EN (1 << 5)
83024b246eSLinus Torvalds # define CIA_CTRL_PCI_REQ64_EN (1 << 6)
84024b246eSLinus Torvalds # define CIA_CTRL_PCI_ACK64_EN (1 << 7)
85024b246eSLinus Torvalds # define CIA_CTRL_ADDR_PE_EN (1 << 8)
86024b246eSLinus Torvalds # define CIA_CTRL_PERR_EN (1 << 9)
87024b246eSLinus Torvalds # define CIA_CTRL_FILL_ERR_EN (1 << 10)
88024b246eSLinus Torvalds # define CIA_CTRL_MCHK_ERR_EN (1 << 11)
89024b246eSLinus Torvalds # define CIA_CTRL_ECC_CHK_EN (1 << 12)
90024b246eSLinus Torvalds # define CIA_CTRL_ASSERT_IDLE_BC (1 << 13)
91024b246eSLinus Torvalds # define CIA_CTRL_COM_IDLE_BC (1 << 14)
92024b246eSLinus Torvalds # define CIA_CTRL_CSR_IOA_BYPASS (1 << 15)
93024b246eSLinus Torvalds # define CIA_CTRL_IO_FLUSHREQ_EN (1 << 16)
94024b246eSLinus Torvalds # define CIA_CTRL_CPU_FLUSHREQ_EN (1 << 17)
95024b246eSLinus Torvalds # define CIA_CTRL_ARB_CPU_EN (1 << 18)
96024b246eSLinus Torvalds # define CIA_CTRL_EN_ARB_LINK (1 << 19)
97024b246eSLinus Torvalds # define CIA_CTRL_RD_TYPE_SHIFT 20
98024b246eSLinus Torvalds # define CIA_CTRL_RL_TYPE_SHIFT 24
99024b246eSLinus Torvalds # define CIA_CTRL_RM_TYPE_SHIFT 28
100024b246eSLinus Torvalds # define CIA_CTRL_EN_DMA_RD_PERF (1 << 31)
101024b246eSLinus Torvalds #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
102024b246eSLinus Torvalds # define CIA_CNFG_IOA_BWEN (1 << 0)
103024b246eSLinus Torvalds # define CIA_CNFG_PCI_MWEN (1 << 4)
104024b246eSLinus Torvalds # define CIA_CNFG_PCI_DWEN (1 << 5)
105024b246eSLinus Torvalds # define CIA_CNFG_PCI_WLEN (1 << 8)
106024b246eSLinus Torvalds #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107024b246eSLinus Torvalds #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108024b246eSLinus Torvalds #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109024b246eSLinus Torvalds #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110024b246eSLinus Torvalds #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
111024b246eSLinus Torvalds # define CIA_CACK_EN_LOCK_EN (1 << 0)
112024b246eSLinus Torvalds # define CIA_CACK_EN_MB_EN (1 << 1)
113024b246eSLinus Torvalds # define CIA_CACK_EN_SET_DIRTY_EN (1 << 2)
114024b246eSLinus Torvalds # define CIA_CACK_EN_BC_VICTIM_EN (1 << 3)
115024b246eSLinus Torvalds
116024b246eSLinus Torvalds
117024b246eSLinus Torvalds /*
118024b246eSLinus Torvalds * 21171-CA Diagnostic Registers
119024b246eSLinus Torvalds */
120024b246eSLinus Torvalds #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
121024b246eSLinus Torvalds #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
122024b246eSLinus Torvalds
123024b246eSLinus Torvalds /*
124024b246eSLinus Torvalds * 21171-CA Performance Monitor registers
125024b246eSLinus Torvalds */
126024b246eSLinus Torvalds #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
127024b246eSLinus Torvalds #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
128024b246eSLinus Torvalds
129024b246eSLinus Torvalds /*
130024b246eSLinus Torvalds * 21171-CA Error registers
131024b246eSLinus Torvalds */
132024b246eSLinus Torvalds #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
133024b246eSLinus Torvalds #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
134024b246eSLinus Torvalds #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
135024b246eSLinus Torvalds # define CIA_ERR_COR_ERR (1 << 0)
136024b246eSLinus Torvalds # define CIA_ERR_UN_COR_ERR (1 << 1)
137024b246eSLinus Torvalds # define CIA_ERR_CPU_PE (1 << 2)
138024b246eSLinus Torvalds # define CIA_ERR_MEM_NEM (1 << 3)
139024b246eSLinus Torvalds # define CIA_ERR_PCI_SERR (1 << 4)
140024b246eSLinus Torvalds # define CIA_ERR_PERR (1 << 5)
141024b246eSLinus Torvalds # define CIA_ERR_PCI_ADDR_PE (1 << 6)
142024b246eSLinus Torvalds # define CIA_ERR_RCVD_MAS_ABT (1 << 7)
143024b246eSLinus Torvalds # define CIA_ERR_RCVD_TAR_ABT (1 << 8)
144024b246eSLinus Torvalds # define CIA_ERR_PA_PTE_INV (1 << 9)
145024b246eSLinus Torvalds # define CIA_ERR_FROM_WRT_ERR (1 << 10)
146024b246eSLinus Torvalds # define CIA_ERR_IOA_TIMEOUT (1 << 11)
147024b246eSLinus Torvalds # define CIA_ERR_LOST_CORR_ERR (1 << 16)
148024b246eSLinus Torvalds # define CIA_ERR_LOST_UN_CORR_ERR (1 << 17)
149024b246eSLinus Torvalds # define CIA_ERR_LOST_CPU_PE (1 << 18)
150024b246eSLinus Torvalds # define CIA_ERR_LOST_MEM_NEM (1 << 19)
151024b246eSLinus Torvalds # define CIA_ERR_LOST_PERR (1 << 21)
152024b246eSLinus Torvalds # define CIA_ERR_LOST_PCI_ADDR_PE (1 << 22)
153024b246eSLinus Torvalds # define CIA_ERR_LOST_RCVD_MAS_ABT (1 << 23)
154024b246eSLinus Torvalds # define CIA_ERR_LOST_RCVD_TAR_ABT (1 << 24)
155024b246eSLinus Torvalds # define CIA_ERR_LOST_PA_PTE_INV (1 << 25)
156024b246eSLinus Torvalds # define CIA_ERR_LOST_FROM_WRT_ERR (1 << 26)
157024b246eSLinus Torvalds # define CIA_ERR_LOST_IOA_TIMEOUT (1 << 27)
158024b246eSLinus Torvalds # define CIA_ERR_VALID (1 << 31)
159024b246eSLinus Torvalds #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
160024b246eSLinus Torvalds #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
161024b246eSLinus Torvalds #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
162024b246eSLinus Torvalds #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
163024b246eSLinus Torvalds #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
164024b246eSLinus Torvalds #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
165024b246eSLinus Torvalds #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
166024b246eSLinus Torvalds #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
167024b246eSLinus Torvalds
168024b246eSLinus Torvalds /*
169024b246eSLinus Torvalds * 21171-CA System configuration registers
170024b246eSLinus Torvalds */
171024b246eSLinus Torvalds #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
172024b246eSLinus Torvalds #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
173024b246eSLinus Torvalds #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
174024b246eSLinus Torvalds #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
175024b246eSLinus Torvalds #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
176024b246eSLinus Torvalds #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
177024b246eSLinus Torvalds #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
178024b246eSLinus Torvalds #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
179024b246eSLinus Torvalds #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
180024b246eSLinus Torvalds #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
181024b246eSLinus Torvalds #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
182024b246eSLinus Torvalds #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
183024b246eSLinus Torvalds
184024b246eSLinus Torvalds /*
185024b246eSLinus Torvalds * 2117A-CA PCI Address and Scatter-Gather Registers.
186024b246eSLinus Torvalds */
187024b246eSLinus Torvalds #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
188024b246eSLinus Torvalds
189024b246eSLinus Torvalds #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
190024b246eSLinus Torvalds #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
191024b246eSLinus Torvalds #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
192024b246eSLinus Torvalds
193024b246eSLinus Torvalds #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
194024b246eSLinus Torvalds #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
195024b246eSLinus Torvalds #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
196024b246eSLinus Torvalds
197024b246eSLinus Torvalds #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
198024b246eSLinus Torvalds #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
199024b246eSLinus Torvalds #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
200024b246eSLinus Torvalds
201024b246eSLinus Torvalds #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
202024b246eSLinus Torvalds #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
203024b246eSLinus Torvalds #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
204024b246eSLinus Torvalds
205024b246eSLinus Torvalds #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
206024b246eSLinus Torvalds #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
207024b246eSLinus Torvalds #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
208024b246eSLinus Torvalds
209024b246eSLinus Torvalds #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
210024b246eSLinus Torvalds
211024b246eSLinus Torvalds /*
212024b246eSLinus Torvalds * 2117A-CA Address Translation Registers.
213024b246eSLinus Torvalds */
214024b246eSLinus Torvalds
215024b246eSLinus Torvalds /* 8 tag registers, the first 4 of which are lockable. */
216024b246eSLinus Torvalds #define CIA_IOC_TB_TAGn(n) \
217024b246eSLinus Torvalds (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
218024b246eSLinus Torvalds
219024b246eSLinus Torvalds /* 4 page registers per tag register. */
220024b246eSLinus Torvalds #define CIA_IOC_TBn_PAGEm(n,m) \
221024b246eSLinus Torvalds (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
222024b246eSLinus Torvalds
223024b246eSLinus Torvalds /*
224024b246eSLinus Torvalds * Memory spaces:
225024b246eSLinus Torvalds */
226024b246eSLinus Torvalds #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
227024b246eSLinus Torvalds #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
228024b246eSLinus Torvalds #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
229024b246eSLinus Torvalds #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
230024b246eSLinus Torvalds #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
231024b246eSLinus Torvalds #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
232024b246eSLinus Torvalds #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
233024b246eSLinus Torvalds #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
234024b246eSLinus Torvalds #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
235024b246eSLinus Torvalds #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
236024b246eSLinus Torvalds #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
237024b246eSLinus Torvalds
238024b246eSLinus Torvalds /*
239024b246eSLinus Torvalds * ALCOR's GRU ASIC registers
240024b246eSLinus Torvalds */
241024b246eSLinus Torvalds #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
242024b246eSLinus Torvalds #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
243024b246eSLinus Torvalds #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
244024b246eSLinus Torvalds #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
245024b246eSLinus Torvalds #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
246024b246eSLinus Torvalds
247024b246eSLinus Torvalds #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
248024b246eSLinus Torvalds #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
249024b246eSLinus Torvalds #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
250024b246eSLinus Torvalds #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
251024b246eSLinus Torvalds
252024b246eSLinus Torvalds #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
253024b246eSLinus Torvalds #define XLT_GRU_INT_REQ_BITS 0x80003fffUL
254024b246eSLinus Torvalds #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
255024b246eSLinus Torvalds
256024b246eSLinus Torvalds /*
257024b246eSLinus Torvalds * PYXIS interrupt control registers
258024b246eSLinus Torvalds */
259024b246eSLinus Torvalds #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
260024b246eSLinus Torvalds #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
261024b246eSLinus Torvalds #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
262024b246eSLinus Torvalds #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
263024b246eSLinus Torvalds #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
264024b246eSLinus Torvalds #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
265024b246eSLinus Torvalds #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
266024b246eSLinus Torvalds #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
267024b246eSLinus Torvalds #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
268024b246eSLinus Torvalds #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
269024b246eSLinus Torvalds
270024b246eSLinus Torvalds /* Offset between ram physical addresses and pci64 DAC bus addresses. */
271024b246eSLinus Torvalds #define PYXIS_DAC_OFFSET (1UL << 40)
272024b246eSLinus Torvalds
273024b246eSLinus Torvalds /*
274024b246eSLinus Torvalds * Data structure for handling CIA machine checks.
275024b246eSLinus Torvalds */
276024b246eSLinus Torvalds
277024b246eSLinus Torvalds /* System-specific info. */
278024b246eSLinus Torvalds struct el_CIA_sysdata_mcheck {
279024b246eSLinus Torvalds unsigned long cpu_err0;
280024b246eSLinus Torvalds unsigned long cpu_err1;
281024b246eSLinus Torvalds unsigned long cia_err;
282024b246eSLinus Torvalds unsigned long cia_stat;
283024b246eSLinus Torvalds unsigned long err_mask;
284024b246eSLinus Torvalds unsigned long cia_syn;
285024b246eSLinus Torvalds unsigned long mem_err0;
286024b246eSLinus Torvalds unsigned long mem_err1;
287024b246eSLinus Torvalds unsigned long pci_err0;
288024b246eSLinus Torvalds unsigned long pci_err1;
289024b246eSLinus Torvalds unsigned long pci_err2;
290024b246eSLinus Torvalds };
291024b246eSLinus Torvalds
292024b246eSLinus Torvalds
293024b246eSLinus Torvalds #ifdef __KERNEL__
294024b246eSLinus Torvalds
295024b246eSLinus Torvalds #ifndef __EXTERN_INLINE
296024b246eSLinus Torvalds /* Do not touch, this should *NOT* be static inline */
297024b246eSLinus Torvalds #define __EXTERN_INLINE extern inline
298024b246eSLinus Torvalds #define __IO_EXTERN_INLINE
299024b246eSLinus Torvalds #endif
300024b246eSLinus Torvalds
301024b246eSLinus Torvalds /*
302024b246eSLinus Torvalds * I/O functions:
303024b246eSLinus Torvalds *
304024b246eSLinus Torvalds * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
305024b246eSLinus Torvalds * series of processors uses a sparse address mapping scheme to
306024b246eSLinus Torvalds * get at PCI memory and I/O.
307024b246eSLinus Torvalds */
308024b246eSLinus Torvalds
309024b246eSLinus Torvalds /*
310024b246eSLinus Torvalds * Memory functions. 64-bit and 32-bit accesses are done through
311024b246eSLinus Torvalds * dense memory space, everything else through sparse space.
312024b246eSLinus Torvalds *
313024b246eSLinus Torvalds * For reading and writing 8 and 16 bit quantities we need to
314024b246eSLinus Torvalds * go through one of the three sparse address mapping regions
315024b246eSLinus Torvalds * and use the HAE_MEM CSR to provide some bits of the address.
316024b246eSLinus Torvalds * The following few routines use only sparse address region 1
317024b246eSLinus Torvalds * which gives 1Gbyte of accessible space which relates exactly
318024b246eSLinus Torvalds * to the amount of PCI memory mapping *into* system address space.
319024b246eSLinus Torvalds * See p 6-17 of the specification but it looks something like this:
320024b246eSLinus Torvalds *
321024b246eSLinus Torvalds * 21164 Address:
322024b246eSLinus Torvalds *
323024b246eSLinus Torvalds * 3 2 1
324024b246eSLinus Torvalds * 9876543210987654321098765432109876543210
325024b246eSLinus Torvalds * 1ZZZZ0.PCI.QW.Address............BBLL
326024b246eSLinus Torvalds *
327024b246eSLinus Torvalds * ZZ = SBZ
328024b246eSLinus Torvalds * BB = Byte offset
329024b246eSLinus Torvalds * LL = Transfer length
330024b246eSLinus Torvalds *
331024b246eSLinus Torvalds * PCI Address:
332024b246eSLinus Torvalds *
333024b246eSLinus Torvalds * 3 2 1
334024b246eSLinus Torvalds * 10987654321098765432109876543210
335024b246eSLinus Torvalds * HHH....PCI.QW.Address........ 00
336024b246eSLinus Torvalds *
337024b246eSLinus Torvalds * HHH = 31:29 HAE_MEM CSR
338024b246eSLinus Torvalds *
339024b246eSLinus Torvalds */
340024b246eSLinus Torvalds
341024b246eSLinus Torvalds #define vip volatile int __force *
342024b246eSLinus Torvalds #define vuip volatile unsigned int __force *
343024b246eSLinus Torvalds #define vulp volatile unsigned long __force *
344024b246eSLinus Torvalds
cia_ioread8(const void __iomem * xaddr)345*e19d4ebcSArnd Bergmann __EXTERN_INLINE u8 cia_ioread8(const void __iomem *xaddr)
346024b246eSLinus Torvalds {
347024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
348024b246eSLinus Torvalds unsigned long result, base_and_type;
349024b246eSLinus Torvalds
350024b246eSLinus Torvalds if (addr >= CIA_DENSE_MEM)
351024b246eSLinus Torvalds base_and_type = CIA_SPARSE_MEM + 0x00;
352024b246eSLinus Torvalds else
353024b246eSLinus Torvalds base_and_type = CIA_IO + 0x00;
354024b246eSLinus Torvalds
355024b246eSLinus Torvalds /* We can use CIA_MEM_R1_MASK for io ports too, since it is large
356024b246eSLinus Torvalds enough to cover all io ports, and smaller than CIA_IO. */
357024b246eSLinus Torvalds addr &= CIA_MEM_R1_MASK;
358024b246eSLinus Torvalds result = *(vip) ((addr << 5) + base_and_type);
359024b246eSLinus Torvalds return __kernel_extbl(result, addr & 3);
360024b246eSLinus Torvalds }
361024b246eSLinus Torvalds
cia_iowrite8(u8 b,void __iomem * xaddr)362024b246eSLinus Torvalds __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
363024b246eSLinus Torvalds {
364024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
365024b246eSLinus Torvalds unsigned long w, base_and_type;
366024b246eSLinus Torvalds
367024b246eSLinus Torvalds if (addr >= CIA_DENSE_MEM)
368024b246eSLinus Torvalds base_and_type = CIA_SPARSE_MEM + 0x00;
369024b246eSLinus Torvalds else
370024b246eSLinus Torvalds base_and_type = CIA_IO + 0x00;
371024b246eSLinus Torvalds
372024b246eSLinus Torvalds addr &= CIA_MEM_R1_MASK;
373024b246eSLinus Torvalds w = __kernel_insbl(b, addr & 3);
374024b246eSLinus Torvalds *(vuip) ((addr << 5) + base_and_type) = w;
375024b246eSLinus Torvalds }
376024b246eSLinus Torvalds
cia_ioread16(const void __iomem * xaddr)377*e19d4ebcSArnd Bergmann __EXTERN_INLINE u16 cia_ioread16(const void __iomem *xaddr)
378024b246eSLinus Torvalds {
379024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
380024b246eSLinus Torvalds unsigned long result, base_and_type;
381024b246eSLinus Torvalds
382024b246eSLinus Torvalds if (addr >= CIA_DENSE_MEM)
383024b246eSLinus Torvalds base_and_type = CIA_SPARSE_MEM + 0x08;
384024b246eSLinus Torvalds else
385024b246eSLinus Torvalds base_and_type = CIA_IO + 0x08;
386024b246eSLinus Torvalds
387024b246eSLinus Torvalds addr &= CIA_MEM_R1_MASK;
388024b246eSLinus Torvalds result = *(vip) ((addr << 5) + base_and_type);
389024b246eSLinus Torvalds return __kernel_extwl(result, addr & 3);
390024b246eSLinus Torvalds }
391024b246eSLinus Torvalds
cia_iowrite16(u16 b,void __iomem * xaddr)392024b246eSLinus Torvalds __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
393024b246eSLinus Torvalds {
394024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
395024b246eSLinus Torvalds unsigned long w, base_and_type;
396024b246eSLinus Torvalds
397024b246eSLinus Torvalds if (addr >= CIA_DENSE_MEM)
398024b246eSLinus Torvalds base_and_type = CIA_SPARSE_MEM + 0x08;
399024b246eSLinus Torvalds else
400024b246eSLinus Torvalds base_and_type = CIA_IO + 0x08;
401024b246eSLinus Torvalds
402024b246eSLinus Torvalds addr &= CIA_MEM_R1_MASK;
403024b246eSLinus Torvalds w = __kernel_inswl(b, addr & 3);
404024b246eSLinus Torvalds *(vuip) ((addr << 5) + base_and_type) = w;
405024b246eSLinus Torvalds }
406024b246eSLinus Torvalds
cia_ioread32(const void __iomem * xaddr)407*e19d4ebcSArnd Bergmann __EXTERN_INLINE u32 cia_ioread32(const void __iomem *xaddr)
408024b246eSLinus Torvalds {
409024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
410024b246eSLinus Torvalds if (addr < CIA_DENSE_MEM)
411024b246eSLinus Torvalds addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
412024b246eSLinus Torvalds return *(vuip)addr;
413024b246eSLinus Torvalds }
414024b246eSLinus Torvalds
cia_iowrite32(u32 b,void __iomem * xaddr)415024b246eSLinus Torvalds __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
416024b246eSLinus Torvalds {
417024b246eSLinus Torvalds unsigned long addr = (unsigned long) xaddr;
418024b246eSLinus Torvalds if (addr < CIA_DENSE_MEM)
419024b246eSLinus Torvalds addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
420024b246eSLinus Torvalds *(vuip)addr = b;
421024b246eSLinus Torvalds }
422024b246eSLinus Torvalds
cia_ioread64(const void __iomem * xaddr)423*e19d4ebcSArnd Bergmann __EXTERN_INLINE u64 cia_ioread64(const void __iomem *xaddr)
424*e19d4ebcSArnd Bergmann {
425*e19d4ebcSArnd Bergmann unsigned long addr = (unsigned long) xaddr;
426*e19d4ebcSArnd Bergmann if (addr < CIA_DENSE_MEM)
427*e19d4ebcSArnd Bergmann addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
428*e19d4ebcSArnd Bergmann return *(vulp)addr;
429*e19d4ebcSArnd Bergmann }
430*e19d4ebcSArnd Bergmann
cia_iowrite64(u64 b,void __iomem * xaddr)431*e19d4ebcSArnd Bergmann __EXTERN_INLINE void cia_iowrite64(u64 b, void __iomem *xaddr)
432*e19d4ebcSArnd Bergmann {
433*e19d4ebcSArnd Bergmann unsigned long addr = (unsigned long) xaddr;
434*e19d4ebcSArnd Bergmann if (addr < CIA_DENSE_MEM)
435*e19d4ebcSArnd Bergmann addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
436*e19d4ebcSArnd Bergmann *(vulp)addr = b;
437*e19d4ebcSArnd Bergmann }
438*e19d4ebcSArnd Bergmann
cia_ioportmap(unsigned long addr)439024b246eSLinus Torvalds __EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
440024b246eSLinus Torvalds {
441024b246eSLinus Torvalds return (void __iomem *)(addr + CIA_IO);
442024b246eSLinus Torvalds }
443024b246eSLinus Torvalds
cia_ioremap(unsigned long addr,unsigned long size)444024b246eSLinus Torvalds __EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
445024b246eSLinus Torvalds unsigned long size)
446024b246eSLinus Torvalds {
447024b246eSLinus Torvalds return (void __iomem *)(addr + CIA_DENSE_MEM);
448024b246eSLinus Torvalds }
449024b246eSLinus Torvalds
cia_is_ioaddr(unsigned long addr)450024b246eSLinus Torvalds __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
451024b246eSLinus Torvalds {
452024b246eSLinus Torvalds return addr >= IDENT_ADDR + 0x8000000000UL;
453024b246eSLinus Torvalds }
454024b246eSLinus Torvalds
cia_is_mmio(const volatile void __iomem * addr)455024b246eSLinus Torvalds __EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
456024b246eSLinus Torvalds {
457024b246eSLinus Torvalds return (unsigned long)addr >= CIA_DENSE_MEM;
458024b246eSLinus Torvalds }
459024b246eSLinus Torvalds
cia_bwx_ioportmap(unsigned long addr)460024b246eSLinus Torvalds __EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
461024b246eSLinus Torvalds {
462024b246eSLinus Torvalds return (void __iomem *)(addr + CIA_BW_IO);
463024b246eSLinus Torvalds }
464024b246eSLinus Torvalds
cia_bwx_ioremap(unsigned long addr,unsigned long size)465024b246eSLinus Torvalds __EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
466024b246eSLinus Torvalds unsigned long size)
467024b246eSLinus Torvalds {
468024b246eSLinus Torvalds return (void __iomem *)(addr + CIA_BW_MEM);
469024b246eSLinus Torvalds }
470024b246eSLinus Torvalds
cia_bwx_is_ioaddr(unsigned long addr)471024b246eSLinus Torvalds __EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
472024b246eSLinus Torvalds {
473024b246eSLinus Torvalds return addr >= IDENT_ADDR + 0x8000000000UL;
474024b246eSLinus Torvalds }
475024b246eSLinus Torvalds
cia_bwx_is_mmio(const volatile void __iomem * addr)476024b246eSLinus Torvalds __EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
477024b246eSLinus Torvalds {
478024b246eSLinus Torvalds return (unsigned long)addr < CIA_BW_IO;
479024b246eSLinus Torvalds }
480024b246eSLinus Torvalds
481024b246eSLinus Torvalds #undef vip
482024b246eSLinus Torvalds #undef vuip
483024b246eSLinus Torvalds #undef vulp
484024b246eSLinus Torvalds
485024b246eSLinus Torvalds #undef __IO_PREFIX
486024b246eSLinus Torvalds #define __IO_PREFIX cia
487024b246eSLinus Torvalds #define cia_trivial_rw_bw 2
488024b246eSLinus Torvalds #define cia_trivial_rw_lq 1
489024b246eSLinus Torvalds #define cia_trivial_io_bw 0
490024b246eSLinus Torvalds #define cia_trivial_io_lq 0
491024b246eSLinus Torvalds #define cia_trivial_iounmap 1
492024b246eSLinus Torvalds #include <asm/io_trivial.h>
493024b246eSLinus Torvalds
494024b246eSLinus Torvalds #undef __IO_PREFIX
495024b246eSLinus Torvalds #define __IO_PREFIX cia_bwx
496024b246eSLinus Torvalds #define cia_bwx_trivial_rw_bw 1
497024b246eSLinus Torvalds #define cia_bwx_trivial_rw_lq 1
498024b246eSLinus Torvalds #define cia_bwx_trivial_io_bw 1
499024b246eSLinus Torvalds #define cia_bwx_trivial_io_lq 1
500024b246eSLinus Torvalds #define cia_bwx_trivial_iounmap 1
501024b246eSLinus Torvalds #include <asm/io_trivial.h>
502024b246eSLinus Torvalds
503024b246eSLinus Torvalds #undef __IO_PREFIX
504024b246eSLinus Torvalds #ifdef CONFIG_ALPHA_PYXIS
505024b246eSLinus Torvalds #define __IO_PREFIX cia_bwx
506024b246eSLinus Torvalds #else
507024b246eSLinus Torvalds #define __IO_PREFIX cia
508024b246eSLinus Torvalds #endif
509024b246eSLinus Torvalds
510024b246eSLinus Torvalds #ifdef __IO_EXTERN_INLINE
511024b246eSLinus Torvalds #undef __EXTERN_INLINE
512024b246eSLinus Torvalds #undef __IO_EXTERN_INLINE
513024b246eSLinus Torvalds #endif
514024b246eSLinus Torvalds
515024b246eSLinus Torvalds #endif /* __KERNEL__ */
516024b246eSLinus Torvalds
517024b246eSLinus Torvalds #endif /* __ALPHA_CIA__H__ */
518