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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLVZInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Predicates = [HasExtLVZ] in {
19 def GCSRRD : FmtCSR<0x05000000, (outs GPR:$rd), (ins uimm14:$csr_num),
23 def GCSRWR : FmtCSR<0x05000020, (outs GPR:$dst),
25 def GCSRXCHG : FmtCSRXCHG<0x05000000, (outs GPR:$dst),
30 def GTLBFLUSH : FmtI32<0x06482401>;
31 def HVCL : MISC_I15<0x002b8000>;
33 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0, Predicates = [HasExtLVZ]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-a5-a113x2-av400.dts21 memory@0 {
23 reg = <0x0 0x0 0x0 0x40000000>;
34 reg = <0x0 0x05000000 0x0 0xa00000>;
H A Damlogic-a4-a113l2-ba400.dts21 memory@0 {
23 reg = <0x0 0x0 0x0 0x40000000>;
34 reg = <0x0 0x05000000 0x0 0xa00000>;
H A Dmeson-s4-s805x2-aq222.dts21 memory@0 {
23 reg = <0x0 0x0 0x0 0x40000000>;
33 reg = <0x0 0x05000000 0x0 0x3400000>;
40 #clock-cells = <0>;
42 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
88 pwms = <&pwm_ij 1 1500 0>;
89 pwm-dutycycle-range = <100 0>;
94 voltage-table = <1049000 0>,
136 pinctrl-0 = <&pwm_e_pins1>;
150 pinctrl-0 = <&remote_pins>;
[all …]
H A Dmeson-gx.dtsi35 hwrom_reserved: hwrom@0 {
36 reg = <0x0 0x0 0x0 0x1000000>;
42 reg = <0x0 0x10000000 0x0 0x200000>;
48 reg = <0x0 0x05000000 0x0 0x300000>;
54 reg = <0x0 0x05300000 0x0 0x2000000>;
61 size = <0x0 0x10000000>;
62 alignment = <0x0 0x400000>;
90 #address-cells = <0x2>;
91 #size-cells = <0x0>;
93 cpu0: cpu@0 {
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_reg.h38 /* PL AXI buses: General Purpose Port #0, M_AXI_GP0. */
39 #define ZYNQ7_PLGP0_HWBASE 0x40000000
40 #define ZYNQ7_PLGP0_SIZE 0x40000000
43 #define ZYNQ7_PLGP1_HWBASE 0x80000000
44 #define ZYNQ7_PLGP1_SIZE 0x40000000
47 #define ZYNQ7_PSIO_HWBASE 0xE0000000
48 #define ZYNQ7_PSIO_SIZE 0x00300000
52 #define ZYNQ7_UART0_SIZE 0x1000
54 #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
55 #define ZYNQ7_UART1_SIZE 0x1000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm53016-dlink-dwl-8610ap.dts13 memory@0 {
16 reg = <0x00000000 0x08000000>,
17 <0x88000000 0x08000000>;
26 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
66 * Flash memory at 0x1e000000-0x1fffffff
72 reg = <0x1e080000 0x00020000>;
112 trx@0 {
114 reg = <0x00000000 0x02800000>;
121 reg = <0x02800000 0x02800000>;
128 reg = <0x05000000 0x03000000>;
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq5.dtsi15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
34 reg = <0x8 0x04000000 0x0 0x1000000>;
37 reg = <0x8 0x05000000 0x0 0x1000000>;
40 reg = <0x8 0x06000000 0x0 0x100000>;
43 reg = <0x8 0x06100000 0x0 0x100000>;
47 reg = <0x8 0x06200000 0x0 0x100000>;
49 mhm_reserved_0: the-mhm-reserved-0@0 {
50 reg = <0x8 0x00000000 0x0 0x0000800>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/ti/
H A Dk3-udma.yaml56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
164 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x0500000
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8992-lg-bullhead.dtsi26 qcom,msm-id = <251 0>, <252 0>;
27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
47 reg = <0x0 0x1ff00000 0x0 0x40000>;
48 console-size = <0x10000>;
49 record-size = <0x10000>;
50 ftrace-size = <0x10000>;
51 pmsg-size = <0x20000>;
55 reg = <0 0x03400000 0 0xc00000>;
60 reg = <0x0 0x05000000 0x0 0x1a00000>;
71 pm8994_regulators: regulators-0 {
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Ds5pv210-aquila.dts32 reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>;
35 pmic_ap_clk: clock-0 {
38 #clock-cells = <0>;
42 vtf_reg: regulator-0 {
67 sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>;
71 #size-cells = <0>;
75 reg = <0x66>;
77 max8998,pmic-buck1-default-dvs-idx = <0>;
83 max8998,pmic-buck2-default-dvs-idx = <0>;
123 regulator-name = "VCC_3.0V";
[all …]
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0c>;
92 reg = <0x10060000 0x100>;
[all …]
H A Ds5pv210-goni.dts33 reg = <0x30000000 0x05000000>,
34 <0x40000000 0x10000000>,
35 <0x50000000 0x08000000>;
38 pmic_ap_clk: clock-0 {
41 #clock-cells = <0>;
45 vtf_reg: regulator-0 {
79 sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>;
83 #size-cells = <0>;
87 reg = <0x66>;
89 max8998,pmic-buck1-default-dvs-idx = <0>;
[all …]
/freebsd/sys/dev/sym/
H A Dsym_defs.h67 #define PCI_VENDOR_NCR 0x1000
78 #define PCI_ID_SYM53C875 0xf
79 #define PCI_ID_SYM53C875_2 0x8f
80 #define PCI_ID_SYM53C885 0xd
81 #define PCI_ID_SYM53C895 0xc
82 #define PCI_ID_SYM53C896 0xb
83 #define PCI_ID_SYM53C895A 0x12
84 #define PCI_ID_LSI53C1010 0x20
85 #define PCI_ID_LSI53C1010_2 0x21
86 #define PCI_ID_LSI53C1510D 0xa
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a100.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
31 reg = <0x1>;
38 reg = <0x2>;
45 reg = <0x3>;
59 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
93 ranges = <0
[all...]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/crypto/krb5/src/lib/crypto/builtin/des/
H A Df_sched.c44 0x00000000, 0x00000010, 0x00001000, 0x00001010,
45 0x00100000, 0x00100010, 0x00101000, 0x00101010
49 0x00000000, 0x00100000, 0x00001000, 0x00101000,
50 0x00000010, 0x00100010, 0x00001010, 0x00101010,
51 0x00000001, 0x00100001, 0x00001001, 0x00101001,
52 0x00000011, 0x00100011, 0x00001011, 0x00101011
56 0x00000000, 0x00000001, 0x00000100, 0x00000101,
57 0x00010000, 0x00010001, 0x00010100, 0x00010101,
58 0x01000000, 0x01000001, 0x01000100, 0x01000101,
59 0x01010000, 0x01010001, 0x01010100, 0x01010101
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Delf20 0 name elf-mips
21 >0 lelong&0xf0000000 0x00000000 MIPS-I
22 >0 lelong&0xf0000000 0x10000000 MIPS-II
23 >0 lelong&0xf0000000 0x20000000 MIPS-III
24 >0 lelong&0xf0000000 0x30000000 MIPS-IV
25 >0 lelong&0xf0000000 0x40000000 MIPS-V
26 >0 lelong&0xf0000000 0x50000000 MIPS32
27 >0 lelong&0xf0000000 0x60000000 MIPS64
28 >0 lelong&0xf0000000 0x70000000 MIPS32 rel2
29 >0 lelong&0xf0000000 0x80000000 MIPS64 rel2
[all …]
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_swp.h44 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80)
67 #define DPAA2_SWP_REV_4000 0x04000000
68 #define DPAA2_SWP_REV_4100 0x04010000
69 #define DPAA2_SWP_REV_4101 0x04010001
70 #define DPAA2_SWP_REV_5000 0x05000000
72 #define DPAA2_SWP_REV_MASK 0xFFFF0000
75 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/
76 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */
77 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */
78 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_init.h114 U8 LUN[8]; /* 0Ch */
125 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
126 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
127 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
129 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
130 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
131 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
133 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
137 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
138 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dhw.h23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
24 #define QCA988X_2_0_DEVICE_ID (0x003c)
25 #define QCA6164_2_1_DEVICE_ID (0x0041)
26 #define QCA6174_2_1_DEVICE_ID (0x003e)
27 #define QCA6174_3_2_DEVICE_ID (0x0042)
28 #define QCA99X0_2_0_DEVICE_ID (0x0040)
29 #define QCA9888_2_0_DEVICE_ID (0x0056)
30 #define QCA9984_1_0_DEVICE_ID (0x0046)
31 #define QCA9377_1_0_DEVICE_ID (0x0042)
32 #define QCA9887_1_0_DEVICE_ID (0x0050)
[all …]

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