Lines Matching +full:0 +full:x05000000
67 #define PCI_VENDOR_NCR 0x1000
78 #define PCI_ID_SYM53C875 0xf
79 #define PCI_ID_SYM53C875_2 0x8f
80 #define PCI_ID_SYM53C885 0xd
81 #define PCI_ID_SYM53C895 0xc
82 #define PCI_ID_SYM53C896 0xb
83 #define PCI_ID_SYM53C895A 0x12
84 #define PCI_ID_LSI53C1010 0x20
85 #define PCI_ID_LSI53C1010_2 0x21
86 #define PCI_ID_LSI53C1510D 0xa
100 #define FE_LED0 (1<<0)
140 #define SYMBIOS_NVRAM_ADDRESS 0x100
144 u_short type; /* 0x0000 */
149 u_char v_major; /* 0x00 */
150 u_char v_minor; /* 0x30 */
161 #define SYMBIOS_TERM_CANT_PROGRAM (0)
165 #define SYMBIOS_RMVBL_NO_SUPPORT (0)
169 u_char num_hba; /* 0x04 */
170 u_char num_devices; /* 0x10 */
171 u_char max_scam_devices; /* 0x04 */
172 u_char num_valid_scam_devices; /* 0x00 */
178 u_short type; /* 4:8xx / 0:nok */
197 u_char bus_width; /* 0x08/0x10 */
206 #define SYMBIOS_SCAM_DEFAULT_METHOD (0)
211 #define SYMBIOS_SCAM_UNKNOWN (0)
220 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
231 #define TEKRAM_93C46_NVRAM_ADDRESS 0
232 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40
254 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
271 #define ISCON 0x10 /* connected to scsi */
272 #define CRST 0x08 /* force reset */
273 #define IARB 0x02 /* immediate arbitration */
276 #define SDU 0x80 /* cmd: disconnect will raise error */
277 #define CHM 0x40 /* sta: chained mode */
278 #define WSS 0x08 /* sta: wide scsi send [W]*/
279 #define WSR 0x01 /* sta: wide scsi received [W]*/
282 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
283 #define ULTRA 0x80 /* cmd: ULTRA enable */
284 /* bits 0-2, 7 rsvd for C1010 */
287 #define RRE 0x40 /* r/w:e enable response to resel. */
288 #define SRE 0x20 /* r/w:e enable response to select */
300 #define CREQ 0x80 /* r/w: SCSI-REQ */
301 #define CACK 0x40 /* r/w: SCSI-ACK */
302 #define CBSY 0x20 /* r/w: SCSI-BSY */
303 #define CSEL 0x10 /* r/w: SCSI-SEL */
304 #define CATN 0x08 /* r/w: SCSI-ATN */
305 #define CMSG 0x04 /* r/w: SCSI-MSG */
306 #define CC_D 0x02 /* r/w: SCSI-C_D */
307 #define CI_O 0x01 /* r/w: SCSI-I_O */
309 /*0a*/ u8 nc_ssid;
311 /*0b*/ u8 nc_sbcl;
313 /*0c*/ u8 nc_dstat;
314 #define DFE 0x80 /* sta: dma fifo empty */
315 #define MDPE 0x40 /* int: master data parity error */
316 #define BF 0x20 /* int: script: bus fault */
317 #define ABRT 0x10 /* int: script: command aborted */
318 #define SSI 0x08 /* int: script: single step */
319 #define SIR 0x04 /* int: script: interrupt instruct. */
320 #define IID 0x01 /* int: script: illegal instruct. */
322 /*0d*/ u8 nc_sstat0;
323 #define ILF 0x80 /* sta: data in SIDL register lsb */
324 #define ORF 0x40 /* sta: data in SODR register lsb */
325 #define OLF 0x20 /* sta: data in SODL register lsb */
326 #define AIP 0x10 /* sta: arbitration in progress */
327 #define LOA 0x08 /* sta: arbitration lost */
328 #define WOA 0x04 /* sta: arbitration won */
329 #define IRST 0x02 /* sta: scsi reset signal */
330 #define SDP 0x01 /* sta: scsi parity signal */
332 /*0e*/ u8 nc_sstat1;
333 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
335 /*0f*/ u8 nc_sstat2;
336 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
337 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
338 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
339 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
340 #define LDSC 0x02 /* sta: disconnect & reconnect */
348 #define CABRT 0x80 /* cmd: abort current operation */
349 #define SRST 0x40 /* mod: reset chip */
350 #define SIGP 0x20 /* r/w: message from host to script */
351 #define SEM 0x10 /* r/w: message between host + script */
352 #define CON 0x08 /* sta: connected to scsi */
353 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
354 #define SIP 0x02 /* sta: scsi-interrupt */
355 #define DIP 0x01 /* sta: host/script interrupt */
365 #define CSIGP 0x40
366 /* bits 0-2,7 rsvd for C1010 */
369 #define FLF 0x08 /* cmd: flush dma fifo */
370 #define CLF 0x04 /* cmd: clear dma fifo */
371 #define FM 0x02 /* mod: fetch pin mode */
372 #define WRIE 0x01 /* mod: write and invalidate enable */
379 #define BDIS 0x80 /* mod: burst disable */
380 #define MPEE 0x08 /* mod: master parity error enable */
383 #define DFS 0x20 /* mod: dma fifo size */
384 /* bits 0-1, 3-7 rsvd for C1010 */
399 #define BL_2 0x80 /* mod: burst length shift value +2 */
400 #define BL_1 0x40 /* mod: burst length shift value +1 */
401 #define ERL 0x08 /* mod: enable read line */
402 #define ERMP 0x04 /* mod: enable read multiple */
403 #define BOF 0x02 /* mod: burst op code fetch */
409 #define CLSE 0x80 /* mod: cache line size enable */
410 #define PFF 0x40 /* cmd: pre-fetch flush */
411 #define PFEN 0x20 /* mod: pre-fetch enable */
412 #define SSM 0x10 /* mod: single step mode */
413 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
414 #define STD 0x04 /* cmd: start dma mode */
415 #define IRQD 0x02 /* mod: irq disable */
416 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
417 /* bits 0-1 rsvd for C1010 */
423 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
424 #define STO 0x0400/* sta: timeout (select) */
425 #define GEN 0x0200/* sta: timeout (general) */
426 #define HTH 0x0100/* sta: timeout (handshake) */
427 #define MA 0x80 /* sta: phase mismatch */
428 #define CMP 0x40 /* sta: arbitration complete */
429 #define SEL 0x20 /* sta: selected by another device */
430 #define RSL 0x10 /* sta: reselected by another device*/
431 #define SGE 0x08 /* sta: gross error (over/underflow)*/
432 #define UDC 0x04 /* sta: unexpected disconnect */
433 #define RST 0x02 /* sta: scsi bus reset detected */
434 #define PAR 0x01 /* sta: scsi parity error */
447 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
448 #define DBLEN 0x08 /* clock doubler running */
449 #define DBLSEL 0x04 /* clock doubler selected */
453 #define ROF 0x40 /* reset scsi offset (after gross error!) */
454 #define EXT 0x02 /* extended filtering */
457 #define TE 0x80 /* c: tolerAnt enable */
458 #define HSC 0x20 /* c: Halt SCSI Clock */
459 #define CSF 0x02 /* c: clear scsi fifo */
463 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
464 #define SMODE_HVD 0x40 /* High Voltage Differential */
465 #define SMODE_SE 0x80 /* Single Ended */
466 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
467 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
468 /* bits 0-5 rsvd for C1010 */
472 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
473 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
474 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
475 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
476 #define DISFC 0x10 /* Disable Auto FIFO Clear */
477 #define DILS 0x02 /* Disable Internal Load/Store */
478 #define DPR 0x01 /* Disable Pipe Req */
481 #define ZMOD 0x80 /* High Impedance Mode */
482 #define DDAC 0x08 /* Disable Dual Address Cycle */
483 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
484 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
485 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
504 #define U3EN 0x80 /* Enable Ultra 3 */
505 #define AIPCKEN 0x40 /* AIP checking enable */
507 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
508 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
509 #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
510 #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
511 /*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
513 #define DISAIP 0x08 /* Disable AIP generation C10-66 only */
535 #define SNDCRC 0x10 /* Send CRC Request */
562 #define SCR_DATA_OUT 0x00000000
563 #define SCR_DATA_IN 0x01000000
564 #define SCR_COMMAND 0x02000000
565 #define SCR_STATUS 0x03000000
566 #define SCR_DT_DATA_OUT 0x04000000
567 #define SCR_DT_DATA_IN 0x05000000
568 #define SCR_MSG_OUT 0x06000000
569 #define SCR_MSG_IN 0x07000000
571 #define SCR_ILG_OUT 0x04000000
572 #define SCR_ILG_IN 0x05000000
592 #define OPC_MOVE 0x08000000
594 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
595 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
596 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
598 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
599 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
600 #define SCR_CHMOV_TBL (0x10000000)
613 * SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
622 #define SCR_SEL_ABS 0x40000000
623 #define SCR_SEL_ABS_ATN 0x41000000
624 #define SCR_SEL_TBL 0x42000000
625 #define SCR_SEL_TBL_ATN 0x43000000
634 #define SCR_JMP_REL 0x04000000
652 #define SCR_WAIT_DISC 0x48000000
653 #define SCR_WAIT_RESEL 0x50000000
668 #define SCR_SET(f) (0x58000000 | (f))
669 #define SCR_CLR(f) (0x60000000 | (f))
671 #define SCR_CARRY 0x00000400
672 #define SCR_TRG 0x00000200
673 #define SCR_ACK 0x00000040
674 #define SCR_ATN 0x00000008
695 #define SCR_NO_FLUSH 0x01000000
697 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
698 #define SCR_COPY_F(n) (0xc0000000 | (n))
707 * << 0 >>
710 * << 0 >>
713 * << 0 >>
720 * offset 0x80. Bit 7 of register offset is stored in
726 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
729 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
732 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
735 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
737 #define SCR_LOAD 0x00000000
738 #define SCR_SHL 0x01000000
739 #define SCR_OR 0x02000000
740 #define SCR_XOR 0x03000000
741 #define SCR_AND 0x04000000
742 #define SCR_SHR 0x05000000
743 #define SCR_ADD 0x06000000
744 #define SCR_ADDC 0x07000000
746 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
751 * << 0 >>
754 * << 0 >>
757 * << 0 >>
760 * << 0 >>
766 SCR_REG_SFBR(reg,SCR_OR,0)
769 SCR_SFBR_REG(reg,SCR_OR,0)
795 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
796 #define SCR_NO_FLUSH2 0x02000000
797 #define SCR_DSA_REL2 0x10000000
800 (0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
803 (0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
807 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
812 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
851 #define SCR_NO_OP 0x80000000
852 #define SCR_JUMP 0x80080000
853 #define SCR_JUMP64 0x80480000
854 #define SCR_JUMPR 0x80880000
855 #define SCR_CALL 0x88080000
856 #define SCR_CALLR 0x88880000
857 #define SCR_RETURN 0x90080000
858 #define SCR_INT 0x98080000
859 #define SCR_INT_FLY 0x98180000
861 #define IFFALSE(arg) (0x00080000 | (arg))
862 #define IFTRUE(arg) (0x00000000 | (arg))
864 #define WHEN(phase) (0x00030000 | (phase))
865 #define IF(phase) (0x00020000 | (phase))
867 #define DATA(D) (0x00040000 | ((D) & 0xff))
868 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
870 #define CARRYSET (0x00200000)
883 #define M_COMPLETE (0x00)
884 #define M_EXTENDED (0x01)
885 #define M_SAVE_DP (0x02)
886 #define M_RESTORE_DP (0x03)
887 #define M_DISCONNECT (0x04)
888 #define M_ID_ERROR (0x05)
889 #define M_ABORT (0x06)
890 #define M_REJECT (0x07)
891 #define M_NOOP (0x08)
892 #define M_PARITY (0x09)
893 #define M_LCOMPLETE (0x0a)
894 #define M_FCOMPLETE (0x0b)
895 #define M_RESET (0x0c)
896 #define M_ABORT_TAG (0x0d)
897 #define M_CLEAR_QUEUE (0x0e)
898 #define M_INIT_REC (0x0f)
899 #define M_REL_REC (0x10)
900 #define M_TERMINATE (0x11)
901 #define M_SIMPLE_TAG (0x20)
902 #define M_HEAD_TAG (0x21)
903 #define M_ORDERED_TAG (0x22)
904 #define M_IGN_RESIDUE (0x23)
905 #define M_IDENTIFY (0x80)
907 #define M_X_MODIFY_DP (0x00)
908 #define M_X_SYNC_REQ (0x01)
909 #define M_X_WIDE_REQ (0x03)
910 #define M_X_PPR_REQ (0x04)
915 #define PPR_OPT_IU (0x01)
916 #define PPR_OPT_DT (0x02)
917 #define PPR_OPT_QAS (0x04)
918 #define PPR_OPT_MASK (0x07)
924 #define S_GOOD (0x00)
925 #define S_CHECK_COND (0x02)
926 #define S_COND_MET (0x04)
927 #define S_BUSY (0x08)
928 #define S_INT (0x10)
929 #define S_INT_COND_MET (0x14)
930 #define S_CONFLICT (0x18)
931 #define S_TERMINATED (0x20)
932 #define S_QUEUE_FULL (0x28)
933 #define S_ILLEGAL (0xff)