Lines Matching +full:0 +full:x05000000
36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
52 #define SPI_START 0x00000100
53 #define SPI_INST_START 0x00000800
54 #define SPI_VPD_ENB 0x00002000
55 #define SPI_LOADER_START 0x00008000
56 #define SPI_CS_HI_MASK 0x00030000
57 #define SPI_CS_HOLD_MASK 0x000C0000
58 #define SPI_CLK_LO_MASK 0x00300000
59 #define SPI_CLK_HI_MASK 0x00C00000
60 #define SPI_CS_SETUP_MASK 0x03000000
61 #define SPI_EPROM_PG_MASK 0x0C000000
69 #define SPI_WAIT_READY 0x10000000
71 #define AGE_SPI_ADDR 0x204 /* 16bits */
73 #define AGE_SPI_DATA 0x208
75 #define AGE_SPI_CONFIG 0x20C
77 #define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */
79 #define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */
81 #define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
83 #define AGE_SPI_OP_RDID 0x213 /* 8bits */
85 #define AGE_SPI_OP_WREN 0x214 /* 8bits */
87 #define AGE_SPI_OP_RDSR 0x215 /* 8bits */
89 #define AGE_SPI_OP_WRSR 0x216 /* 8bits */
91 #define AGE_SPI_OP_READ 0x217 /* 8bits */
93 #define AGE_TWSI_CTRL 0x218
94 #define TWSI_CTRL_SW_LD_START 0x00000800
95 #define TWSI_CTRL_HW_LD_START 0x00001000
96 #define TWSI_CTRL_LD_EXIST 0x00400000
98 #define AGE_DEV_MISC_CTRL 0x21C
100 #define AGE_MASTER_CFG 0x1400
101 #define MASTER_RESET 0x00000001
102 #define MASTER_MTIMER_ENB 0x00000002
103 #define MASTER_ITIMER_ENB 0x00000004
104 #define MASTER_MANUAL_INT_ENB 0x00000008
105 #define MASTER_CHIP_REV_MASK 0x00FF0000
106 #define MASTER_CHIP_ID_MASK 0xFF000000
114 #define AGE_MANUAL_TIMER 0x1404
116 #define AGE_IM_TIMER 0x1408 /* 16bits */
117 #define AGE_IM_TIMER_MIN 0
121 #define AGE_GPHY_CTRL 0x140C /* 16bits */
122 #define GPHY_CTRL_RST 0x0000
123 #define GPHY_CTRL_CLR 0x0001
125 #define AGE_INTR_CLR_TIMER 0x140E /* 16bits */
127 #define AGE_IDLE_STATUS 0x1410
128 #define IDLE_STATUS_RXMAC 0x00000001
129 #define IDLE_STATUS_TXMAC 0x00000002
130 #define IDLE_STATUS_RXQ 0x00000004
131 #define IDLE_STATUS_TXQ 0x00000008
132 #define IDLE_STATUS_DMARD 0x00000010
133 #define IDLE_STATUS_DMAWR 0x00000020
134 #define IDLE_STATUS_SMB 0x00000040
135 #define IDLE_STATUS_CMB 0x00000080
137 #define AGE_MDIO 0x1414
138 #define MDIO_DATA_MASK 0x0000FFFF
139 #define MDIO_REG_ADDR_MASK 0x001F0000
140 #define MDIO_OP_READ 0x00200000
141 #define MDIO_OP_WRITE 0x00000000
142 #define MDIO_SUP_PREAMBLE 0x00400000
143 #define MDIO_OP_EXECUTE 0x00800000
144 #define MDIO_CLK_25_4 0x00000000
145 #define MDIO_CLK_25_6 0x02000000
146 #define MDIO_CLK_25_8 0x03000000
147 #define MDIO_CLK_25_10 0x04000000
148 #define MDIO_CLK_25_14 0x05000000
149 #define MDIO_CLK_25_20 0x06000000
150 #define MDIO_CLK_25_28 0x07000000
151 #define MDIO_OP_BUSY 0x08000000
152 #define MDIO_DATA_SHIFT 0
158 #define AGE_PHY_ADDR 0
160 #define AGE_PHY_STATUS 0x1418
162 #define AGE_BIST0 0x141C
163 #define BIST0_ENB 0x00000001
164 #define BIST0_SRAM_FAIL 0x00000002
165 #define BIST0_FUSE_FLAG 0x00000004
167 #define AGE_BIST1 0x1420
168 #define BIST1_ENB 0x00000001
169 #define BIST1_SRAM_FAIL 0x00000002
170 #define BIST1_FUSE_FLAG 0x00000004
172 #define AGE_MAC_CFG 0x1480
173 #define MAC_CFG_TX_ENB 0x00000001
174 #define MAC_CFG_RX_ENB 0x00000002
175 #define MAC_CFG_TX_FC 0x00000004
176 #define MAC_CFG_RX_FC 0x00000008
177 #define MAC_CFG_LOOP 0x00000010
178 #define MAC_CFG_FULL_DUPLEX 0x00000020
179 #define MAC_CFG_TX_CRC_ENB 0x00000040
180 #define MAC_CFG_TX_AUTO_PAD 0x00000080
181 #define MAC_CFG_TX_LENCHK 0x00000100
182 #define MAC_CFG_RX_JUMBO_ENB 0x00000200
183 #define MAC_CFG_PREAMBLE_MASK 0x00003C00
184 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000
185 #define MAC_CFG_PROMISC 0x00008000
186 #define MAC_CFG_TX_PAUSE 0x00010000
187 #define MAC_CFG_SCNT 0x00020000
188 #define MAC_CFG_SYNC_RST_TX 0x00040000
189 #define MAC_CFG_SPEED_MASK 0x00300000
190 #define MAC_CFG_SPEED_10_100 0x00100000
191 #define MAC_CFG_SPEED_1000 0x00200000
192 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000
193 #define MAC_CFG_TX_JUMBO_ENB 0x00800000
194 #define MAC_CFG_RXCSUM_ENB 0x01000000
195 #define MAC_CFG_ALLMULTI 0x02000000
196 #define MAC_CFG_BCAST 0x04000000
197 #define MAC_CFG_DBG 0x08000000
201 #define AGE_IPG_IFG_CFG 0x1484
202 #define IPG_IFG_IPGT_MASK 0x0000007F
203 #define IPG_IFG_MIFG_MASK 0x0000FF00
204 #define IPG_IFG_IPG1_MASK 0x007F0000
205 #define IPG_IFG_IPG2_MASK 0x7F000000
206 #define IPG_IFG_IPGT_SHIFT 0
207 #define IPG_IFG_IPGT_DEFAULT 0x60
209 #define IPG_IFG_MIFG_DEFAULT 0x50
211 #define IPG_IFG_IPG1_DEFAULT 0x40
213 #define IPG_IFG_IPG2_DEFAULT 0x60
216 #define AGE_PAR0 0x1488
217 #define AGE_PAR1 0x148C
220 #define AGE_MAR0 0x1490
221 #define AGE_MAR1 0x1494
224 #define AGE_HDPX_CFG 0x1498
225 #define HDPX_CFG_LCOL_MASK 0x000003FF
226 #define HDPX_CFG_RETRY_MASK 0x0000F000
227 #define HDPX_CFG_EXC_DEF_EN 0x00010000
228 #define HDPX_CFG_NO_BACK_C 0x00020000
229 #define HDPX_CFG_NO_BACK_P 0x00040000
230 #define HDPX_CFG_ABEBE 0x00080000
231 #define HDPX_CFG_ABEBT_MASK 0x00F00000
232 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
233 #define HDPX_CFG_LCOL_SHIFT 0
234 #define HDPX_CFG_LCOL_DEFAULT 0x37
236 #define HDPX_CFG_RETRY_DEFAULT 0x0F
238 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
240 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
242 #define AGE_FRAME_SIZE 0x149C
244 #define AGE_WOL_CFG 0x14A0
245 #define WOL_CFG_PATTERN 0x00000001
246 #define WOL_CFG_PATTERN_ENB 0x00000002
247 #define WOL_CFG_MAGIC 0x00000004
248 #define WOL_CFG_MAGIC_ENB 0x00000008
249 #define WOL_CFG_LINK_CHG 0x00000010
250 #define WOL_CFG_LINK_CHG_ENB 0x00000020
251 #define WOL_CFG_PATTERN_DET 0x00000100
252 #define WOL_CFG_MAGIC_DET 0x00000200
253 #define WOL_CFG_LINK_CHG_DET 0x00000400
254 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
255 #define WOL_CFG_PATTERN0 0x00010000
256 #define WOL_CFG_PATTERN1 0x00020000
257 #define WOL_CFG_PATTERN2 0x00040000
258 #define WOL_CFG_PATTERN3 0x00080000
259 #define WOL_CFG_PATTERN4 0x00100000
260 #define WOL_CFG_PATTERN5 0x00200000
261 #define WOL_CFG_PATTERN6 0x00400000
264 #define AGE_PATTERN_CFG0 0x14A4
265 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
266 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
267 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
268 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
270 #define AGE_PATTERN_CFG1 0x14A8
271 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
272 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
273 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
275 #define AGE_SRAM_RD_ADDR 0x1500
277 #define AGE_SRAM_RD_LEN 0x1504
279 #define AGE_SRAM_RRD_ADDR 0x1508
281 #define AGE_SRAM_RRD_LEN 0x150C
283 #define AGE_SRAM_TPD_ADDR 0x1510
285 #define AGE_SRAM_TPD_LEN 0x1514
287 #define AGE_SRAM_TRD_ADDR 0x1518
289 #define AGE_SRAM_TRD_LEN 0x151C
291 #define AGE_SRAM_RX_FIFO_ADDR 0x1520
293 #define AGE_SRAM_RX_FIFO_LEN 0x1524
295 #define AGE_SRAM_TX_FIFO_ADDR 0x1528
297 #define AGE_SRAM_TX_FIFO_LEN 0x152C
299 #define AGE_SRAM_TCPH_ADDR 0x1530
300 #define SRAM_TCPH_ADDR_MASK 0x00000FFF
301 #define SRAM_PATH_ADDR_MASK 0x0FFF0000
302 #define SRAM_TCPH_ADDR_SHIFT 0
305 #define AGE_DMA_BLOCK 0x1534
306 #define DMA_BLOCK_LOAD 0x00000001
311 #define AGE_DESC_ADDR_HI 0x1540
313 #define AGE_DESC_RD_ADDR_LO 0x1544
315 #define AGE_DESC_RRD_ADDR_LO 0x1548
317 #define AGE_DESC_TPD_ADDR_LO 0x154C
319 #define AGE_DESC_CMB_ADDR_LO 0x1550
321 #define AGE_DESC_SMB_ADDR_LO 0x1554
323 #define AGE_DESC_RRD_RD_CNT 0x1558
324 #define DESC_RD_CNT_MASK 0x000007FF
325 #define DESC_RRD_CNT_MASK 0x07FF0000
326 #define DESC_RD_CNT_SHIFT 0
329 #define AGE_DESC_TPD_CNT 0x155C
330 #define DESC_TPD_CNT_MASK 0x00003FF
331 #define DESC_TPD_CNT_SHIFT 0
333 #define AGE_TXQ_CFG 0x1580
334 #define TXQ_CFG_TPD_BURST_MASK 0x0000001F
335 #define TXQ_CFG_ENB 0x00000020
336 #define TXQ_CFG_ENHANCED_MODE 0x00000040
337 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
338 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
339 #define TXQ_CFG_TPD_BURST_SHIFT 0
346 #define AGE_TX_JUMBO_TPD_TH_IPG 0x1584
347 #define TX_JUMBO_TPD_TH_MASK 0x000007FF
348 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000
349 #define TX_JUMBO_TPD_TH_SHIFT 0
353 #define AGE_RXQ_CFG 0x15A0
354 #define RXQ_CFG_RD_BURST_MASK 0x000000FF
355 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
356 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
357 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
358 #define RXQ_CFG_ENB 0x80000000
359 #define RXQ_CFG_RD_BURST_SHIFT 0
366 #define AGE_RXQ_JUMBO_CFG 0x15A4
367 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF
368 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800
369 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000
370 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0
372 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01
375 #define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8
376 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
377 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000
378 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0
381 #define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC
382 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
383 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
384 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0
387 #define AGE_DMA_CFG 0x15C0
388 #define DMA_CFG_IN_ORDER 0x00000001
389 #define DMA_CFG_ENH_ORDER 0x00000002
390 #define DMA_CFG_OUT_ORDER 0x00000004
391 #define DMA_CFG_RCB_64 0x00000000
392 #define DMA_CFG_RCB_128 0x00000008
393 #define DMA_CFG_RD_BURST_128 0x00000000
394 #define DMA_CFG_RD_BURST_256 0x00000010
395 #define DMA_CFG_RD_BURST_512 0x00000020
396 #define DMA_CFG_RD_BURST_1024 0x00000030
397 #define DMA_CFG_RD_BURST_2048 0x00000040
398 #define DMA_CFG_RD_BURST_4096 0x00000050
399 #define DMA_CFG_WR_BURST_128 0x00000000
400 #define DMA_CFG_WR_BURST_256 0x00000080
401 #define DMA_CFG_WR_BURST_512 0x00000100
402 #define DMA_CFG_WR_BURST_1024 0x00000180
403 #define DMA_CFG_WR_BURST_2048 0x00000200
404 #define DMA_CFG_WR_BURST_4096 0x00000280
405 #define DMA_CFG_RD_ENB 0x00000400
406 #define DMA_CFG_WR_ENB 0x00000800
407 #define DMA_CFG_RD_BURST_MASK 0x07
409 #define DMA_CFG_WR_BURST_MASK 0x07
412 #define AGE_CSMB_CTRL 0x15D0
413 #define CSMB_CTRL_CMB_KICK 0x00000001
414 #define CSMB_CTRL_SMB_KICK 0x00000002
415 #define CSMB_CTRL_CMB_ENB 0x00000004
416 #define CSMB_CTRL_SMB_ENB 0x00000008
419 #define AGE_CMB_WR_THRESH 0x15D4
420 #define CMB_WR_THRESH_RRD_MASK 0x000007FF
421 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000
422 #define CMB_WR_THRESH_RRD_SHIFT 0
428 #define AGE_CMB_WR_TIMER 0x15D8
429 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF
430 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000
431 #define CMB_WR_TIMER_RX_SHIFT 0
435 #define AGE_CMB_RX_PKT_CNT 0x15DC
438 #define AGE_CMB_TX_PKT_CNT 0x15E0
441 #define AGE_SMB_TIMER 0x15E4
443 #define AGE_MBOX 0x15F0
444 #define MBOX_RD_PROD_IDX_MASK 0x000007FF
445 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800
446 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000
447 #define MBOX_RD_PROD_IDX_SHIFT 0
451 #define AGE_INTR_STATUS 0x1600
452 #define INTR_SMB 0x00000001
453 #define INTR_MOD_TIMER 0x00000002
454 #define INTR_MANUAL_TIMER 0x00000004
455 #define INTR_RX_FIFO_OFLOW 0x00000008
456 #define INTR_RD_UNDERRUN 0x00000010
457 #define INTR_RRD_OFLOW 0x00000020
458 #define INTR_TX_FIFO_UNDERRUN 0x00000040
459 #define INTR_LINK_CHG 0x00000080
460 #define INTR_HOST_RD_UNDERRUN 0x00000100
461 #define INTR_HOST_RRD_OFLOW 0x00000200
462 #define INTR_DMA_RD_TO_RST 0x00000400
463 #define INTR_DMA_WR_TO_RST 0x00000800
464 #define INTR_GPHY 0x00001000
465 #define INTR_RX_PKT 0x00010000
466 #define INTR_TX_PKT 0x00020000
467 #define INTR_TX_DMA 0x00040000
468 #define INTR_RX_DMA 0x00080000
469 #define INTR_CMB_RX 0x00100000
470 #define INTR_CMB_TX 0x00200000
471 #define INTR_MAC_RX 0x00400000
472 #define INTR_MAC_TX 0x00800000
473 #define INTR_UNDERRUN 0x01000000
474 #define INTR_FRAME_ERROR 0x02000000
475 #define INTR_FRAME_OK 0x04000000
476 #define INTR_CSUM_ERROR 0x08000000
477 #define INTR_PHY_LINK_DOWN 0x10000000
478 #define INTR_DIS_SMB 0x20000000
479 #define INTR_DIS_DMA 0x40000000
480 #define INTR_DIS_INT 0x80000000
483 #define AGE_INTR_MASK 0x1604
549 #define RRD_PROD_MASK 0x0000FFFF
550 #define RD_CONS_MASK 0xFFFF0000
551 #define RRD_PROD_SHIFT 0
554 #define CMB_UPDATED 0x00000001
555 #define TPD_CONS_MASK 0xFFFF0000
562 #define AGE_RRD_NSEGS_MASK 0x000000FF
563 #define AGE_RRD_CONS_MASK 0xFFFF0000
564 #define AGE_RRD_NSEGS_SHIFT 0
567 #define AGE_RRD_CSUM_MASK 0x0000FFFF
568 #define AGE_RRD_LEN_MASK 0xFFFF0000
569 #define AGE_RRD_CSUM_SHIFT 0
572 #define AGE_RRD_ETHERNET 0x00000080
573 #define AGE_RRD_VLAN 0x00000100
574 #define AGE_RRD_ERROR 0x00000200
575 #define AGE_RRD_IPV4 0x00000400
576 #define AGE_RRD_UDP 0x00000800
577 #define AGE_RRD_TCP 0x00001000
578 #define AGE_RRD_BCAST 0x00002000
579 #define AGE_RRD_MCAST 0x00004000
580 #define AGE_RRD_PAUSE 0x00008000
581 #define AGE_RRD_CRC 0x00010000
582 #define AGE_RRD_CODE 0x00020000
583 #define AGE_RRD_DRIBBLE 0x00040000
584 #define AGE_RRD_RUNT 0x00080000
585 #define AGE_RRD_OFLOW 0x00100000
586 #define AGE_RRD_TRUNC 0x00200000
587 #define AGE_RRD_IPCSUM_NOK 0x00400000
588 #define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000
589 #define AGE_RRD_LENGTH_NOK 0x01000000
590 #define AGE_RRD_DES_ADDR_FILTERED 0x02000000
592 #define AGE_RRD_VLAN_MASK 0xFFFF0000
613 #define AGE_RD_LEN_MASK 0x0000FFFF
614 #define AGE_CONS_UPD_REQ_MASK 0xFFFF0000
615 #define AGE_RD_LEN_SHIFT 0
623 #define AGE_TD_VLAN_MASK 0xFFFF0000
624 #define AGE_TD_PKT_INT 0x00008000
625 #define AGE_TD_DMA_INT 0x00004000
626 #define AGE_TD_BUFLEN_MASK 0x00003FFF
630 #define AGE_TD_BUFLEN_SHIFT 0
634 #define AGE_TD_TSO_MSS 0xFFF80000
635 #define AGE_TD_TSO_HDR 0x00040000
636 #define AGE_TD_TSO_TCPHDR_LEN 0x0003C000
637 #define AGE_TD_IPHDR_LEN 0x00003C00
638 #define AGE_TD_LLC_SNAP 0x00000200
639 #define AGE_TD_VLAN_TAGGED 0x00000100
640 #define AGE_TD_UDPCSUM 0x00000080
641 #define AGE_TD_TCPCSUM 0x00000040
642 #define AGE_TD_IPCSUM 0x00000020
643 #define AGE_TD_TSO_IPV4 0x00000010
644 #define AGE_TD_TSO_IPV6 0x00000012
645 #define AGE_TD_CSUM 0x00000008
646 #define AGE_TD_INSERT_VLAN_TAG 0x00000004
647 #define AGE_TD_COALESCE 0x00000002
648 #define AGE_TD_EOP 0x00000001
650 #define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000
651 #define AGE_TD_CSUM_XSUMOFFSET 0xFF000000