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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dnvidia,tegra186-hsp.txt50 - bits 23.. 0:
63 reg = <0x0 0x03c00000 0x0 0xa0000>;
H A Dnvidia,tegra186-hsp.yaml34 - bits 7..0:
51 - bits 23..0:
63 pattern: "^hsp@[0-9a-f]+$"
89 - pattern: "^shared[0-7]$"
90 - pattern: "^shared[0-7]$"
91 - pattern: "^shared[0-7]$"
92 - pattern: "^shared[0-7]$"
93 - pattern: "^shared[0-7]$"
94 - pattern: "^shared[0-7]$"
95 - pattern: "^shared[0-7]$"
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
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/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_chan.c69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | in r12a_write_txpower_ht()
99 /* 1SS, MCS 0..3 */ in r12a_write_txpower_vht()
101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) | in r12a_write_txpower_vht()
102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) | in r12a_write_txpower_vht()
103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) | in r12a_write_txpower_vht()
104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)])); in r12a_write_txpower_vht()
108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) | in r12a_write_txpower_vht()
109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) | in r12a_write_txpower_vht()
110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) | in r12a_write_txpower_vht()
111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)])); in r12a_write_txpower_vht()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml147 reg = <0x03c00000 0xa0000>;
155 reg = <0x30000000 0x50000>;
158 ranges = <0x0 0x30000000 0x50000>;
161 reg = <0x4e000 0x100
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml19 const: 0
122 port@0:
134 "^endpoint(@[0-9])$":
154 - port@0
382 reg = <0x01c0c000 0x1000>;
393 #clock-cells = <0>;
398 #size-cells = <0>;
400 port@0 {
402 #size-cells = <0>;
403 reg = <0>;
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dtargaddrs.h25 #define QCA988X_HOST_INTEREST_ADDRESS 0x00400800
26 #define HOST_INTEREST_MAX_SIZE 0x200
39 u32 hi_app_host_interest; /* 0x00 */
42 u32 hi_failure_state; /* 0x04 */
45 u32 hi_dbglog_hdr; /* 0x08 */
47 u32 hi_unused0c; /* 0x0c */
53 u32 hi_option_flag; /* 0x10 */
59 u32 hi_serial_enable; /* 0x14 */
62 u32 hi_dset_list_head; /* 0x18 */
65 u32 hi_app_start; /* 0x1c */
[all …]
/freebsd/sys/dev/ata/chipsets/
H A Data-siliconimage.c64 #define SII_INTR 0x01
65 #define SII_SETCLK 0x02
66 #define SII_BUG 0x04
67 #define SII_4CH 0x08
77 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, in ata_sii_probe()
78 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, in ata_sii_probe()
79 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, in ata_sii_probe()
80 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, in ata_sii_probe()
81 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, in ata_sii_probe()
82 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, in ata_sii_probe()
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun9i-a80.dtsi65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
H A Dar9300_misc.c37 *hangs = 0; in ar9300_get_hw_hangs()
39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) in ar9300_get_hw_hangs()
50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) in ar9300_get_hw_hangs()
69 #if 0 in ar9300_mac_to_usec()
84 #if 0 in ar9300_mac_to_clks()
145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { in ar9300_set_regulatory_domain()
151 #if 0 in ar9300_set_regulatory_domain()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x220000
[all...]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x
[all...]
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>,
35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>,
43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/freebsd/sys/dev/pms/freebsd/driver/ini/src/
H A Dagtiapi.c92 STATIC U32 agtiapi_intx_mode = 0;
93 STATIC U08 ag_Perbi = 0;
94 STATIC U32 agtiapi_polling_mode = 0;
95 STATIC U32 ag_card_good = 0; // * total card initialized
96 STATIC U32 ag_option_flag = 0; // * adjustable parameter flag
101 S32 ag_encryption_enable = 0;
106 #define PMCoffsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
159 #define AG_LOCAL_FLAGS(_flags) unsigned long _flags = 0
240 U32 maxTargets = 0;
241 U32 ag_portal_count = 0;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV()
47 ::memset(&reg_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV()
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0; in CountITSize()
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x0000000
[all...]