Lines Matching +full:0 +full:x03c00000
64 #define SII_INTR 0x01
65 #define SII_SETCLK 0x02
66 #define SII_BUG 0x04
67 #define SII_4CH 0x08
77 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, in ata_sii_probe()
78 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, in ata_sii_probe()
79 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, in ata_sii_probe()
80 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, in ata_sii_probe()
81 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, in ata_sii_probe()
82 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, in ata_sii_probe()
83 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, in ata_sii_probe()
84 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, in ata_sii_probe()
85 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, in ata_sii_probe()
86 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, in ata_sii_probe()
87 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, in ata_sii_probe()
88 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, in ata_sii_probe()
89 { 0, 0, 0, 0, 0, 0}}; in ata_sii_probe()
117 (pci_read_config(dev, 0x8a, 1) & 1)) in ata_sii_chipinit()
122 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) in ata_sii_chipinit()
123 pci_write_config(dev, 0x8a, in ata_sii_chipinit()
124 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); in ata_sii_chipinit()
125 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) in ata_sii_chipinit()
132 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); in ata_sii_chipinit()
137 pci_write_config(dev, 0x48, in ata_sii_chipinit()
138 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); in ata_sii_chipinit()
141 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); in ata_sii_chipinit()
158 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { in ata_sii_chipinit()
164 pci_write_config(dev, 0x71, 0x01, 1); in ata_sii_chipinit()
171 return 0; in ata_sii_chipinit()
189 return 0; in ata_cmd_ch_attach()
198 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & in ata_cmd_status()
199 (ch->unit ? 0x08 : 0x04))) { in ata_cmd_status()
200 pci_write_config(device_get_parent(dev), 0x71, in ata_cmd_status()
201 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); in ata_cmd_status()
204 return 0; in ata_cmd_status()
214 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); in ata_cmd_setmode()
215 int ureg = ch->unit ? 0x7b : 0x73; in ata_cmd_setmode()
218 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; in ata_cmd_setmode()
220 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, in ata_cmd_setmode()
221 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; in ata_cmd_setmode()
227 umode &= ~(target == 0 ? 0x35 : 0xca); in ata_cmd_setmode()
234 ~(target == 0 ? 0x35 : 0xca), 1); in ata_cmd_setmode()
251 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); in ata_sii_ch_attach()
254 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); in ata_sii_ch_attach()
259 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); in ata_sii_ch_attach()
261 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); in ata_sii_ch_attach()
263 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); in ata_sii_ch_attach()
267 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); in ata_sii_ch_attach()
269 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); in ata_sii_ch_attach()
271 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); in ata_sii_ch_attach()
277 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); in ata_sii_ch_attach()
293 return 0; in ata_sii_ch_attach()
301 return (0); in ata_sii_ch_detach()
314 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) in ata_sii_status()
317 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) in ata_sii_status()
320 return 0; in ata_sii_status()
332 val = ATA_INL(ctlr->r_res2, 0x14c + offset); in ata_sii_reset()
333 if ((val & 0x3) == 0x1) in ata_sii_reset()
334 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); in ata_sii_reset()
339 ch->devices = 0; in ata_sii_reset()
349 int mreg = ch->unit ? 0x84 : 0x80; in ata_sii_setmode()
350 int mask = 0x03 << (target << 2); in ata_sii_setmode()
353 u_int8_t preg = 0xa4 + rego; in ata_sii_setmode()
354 u_int8_t dreg = 0xa8 + rego; in ata_sii_setmode()
355 u_int8_t ureg = 0xac + rego; in ata_sii_setmode()
357 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; in ata_sii_setmode()
358 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; in ata_sii_setmode()
360 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; in ata_sii_setmode()
366 (pci_read_config(parent, 0x79, 1) & in ata_sii_setmode()
367 (ch->unit ? 0x02 : 0x01))) { in ata_sii_setmode()
374 mval | (0x03 << (target << 2)), 1); in ata_sii_setmode()
376 (pci_read_config(parent, ureg, 1) & ~0x3f) | in ata_sii_setmode()
381 mval | (0x02 << (target << 2)), 1); in ata_sii_setmode()
387 mval | (0x01 << (target << 2)), 1); in ata_sii_setmode()