69 	    SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) |  in r12a_write_txpower_ht()
99 	/* 1SS, MCS 0..3 */  in r12a_write_txpower_vht()
101 	    SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) |  in r12a_write_txpower_vht()
102 	    SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) |  in r12a_write_txpower_vht()
103 	    SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) |  in r12a_write_txpower_vht()
104 	    SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)]));  in r12a_write_txpower_vht()
108 	    SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) |  in r12a_write_txpower_vht()
109 	    SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) |  in r12a_write_txpower_vht()
110 	    SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) |  in r12a_write_txpower_vht()
111 	    SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)]));  in r12a_write_txpower_vht()
116 		    SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |  in r12a_write_txpower_vht()
117 		    SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |  in r12a_write_txpower_vht()
118 		    SM(R12A_TXAGC_NSS2_MCS0, 0) |  in r12a_write_txpower_vht()
119 		    SM(R12A_TXAGC_NSS2_MCS1, 0));  in r12a_write_txpower_vht()
122 		    SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |  in r12a_write_txpower_vht()
123 		    SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |  in r12a_write_txpower_vht()
124 		    SM(R12A_TXAGC_NSS2_MCS0, power[RTWN_RIDX_VHT_MCS(1, 0)]) |  in r12a_write_txpower_vht()
191 	write_data = 0;  in r12a_tx_power_training()
194 	for (i = 0; i < 3; i++) {  in r12a_tx_power_training()
195 		if (i == 0)  in r12a_tx_power_training()
206 		write_data |= ((power_level & 0xff) << (i * 8));  in r12a_tx_power_training()
210 	    0x00ffffff, write_data);  in r12a_tx_power_training()
234 		if (chan <= 2)			group = 0;  in r12a_get_power_group()
240 			KASSERT(0, ("wrong 2GHz channel %d!\n", chan));  in r12a_get_power_group()
247 		if (chan <= 42)			group = 0;  in r12a_get_power_group()
262 			KASSERT(0, ("wrong 5GHz channel %d!\n", chan));  in r12a_get_power_group()
266 		KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));  in r12a_get_power_group()
300 			power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];  in r12a_get_txpower()
302 		for (i = 0; i < sc->ntxchains; i++) {  in r12a_get_txpower()
329 			power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0];  in r12a_get_txpower()
331 		for (i = 0; i < sc->ntxchains; i++) {  in r12a_get_txpower()
350 			for (ridx = RTWN_RIDX_VHT_MCS(i, 0);  in r12a_get_txpower()
363 	for (ridx = RTWN_RIDX_VHT_MCS(0, 0);  in r12a_get_txpower()
376 		/* TODO: dump VHT 0..9 for each spatial stream */  in r12a_get_txpower()
387 	for (i = 0; i < sc->ntxchains; i++) {  in r12a_set_txpower()
388 		memset(power, 0, sizeof(power));  in r12a_set_txpower()
404 			rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);  in r12a_fix_spur()
405 			rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);  in r12a_fix_spur()
407 			rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);  in r12a_fix_spur()
413 				rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);  in r12a_fix_spur()
415 				    0, 0x40000000);  in r12a_fix_spur()
420 				    0, 0x40000000);  in r12a_fix_spur()
423 				rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);  in r12a_fix_spur()
425 				    0x40000000, 0);  in r12a_fix_spur()
434 			rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);  in r12a_fix_spur()
436 			rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);  in r12a_fix_spur()
465 		KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags));  in r12a_set_band()
470 	for (i = 0; i < 2; i++) {  in r12a_set_band()
471 		uint16_t val = 0;  in r12a_set_band()
473 		switch ((swing >> i * 2) & 0x3) {  in r12a_set_band()
474 		case 0:  in r12a_set_band()
475 			val = 0x200;	/* 0 dB	*/  in r12a_set_band()
478 			val = 0x16a;	/* -3 dB */  in r12a_set_band()
481 			val = 0x101;	/* -6 dB */  in r12a_set_band()
484 			val = 0xb6;	/* -9 dB */  in r12a_set_band()
504 		val = 0x09280000;  in r12a_set_chan()
506 		val = 0x08a60000;  in r12a_set_chan()
508 		val = 0x08a40000;  in r12a_set_chan()
510 		val = 0x08240000;  in r12a_set_chan()
512 		val = 0x12d40000;  in r12a_set_chan()
514 	rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);  in r12a_set_chan()
516 	for (i = 0; i < sc->nrxchains; i++) {  in r12a_set_chan()
518 			val = 0x10100;  in r12a_set_chan()
520 			val = 0x30100;  in r12a_set_chan()
522 			val = 0x50100;  in r12a_set_chan()
524 			val = 0x00000;  in r12a_set_chan()
526 		rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val);  in r12a_set_chan()
531 		KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan));  in r12a_set_chan()
532 		rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan);  in r12a_set_chan()
536 		uint8_t ext20 = 0, ext40 = 0;  in r12a_set_chan()
560 		rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0x100);  in r12a_set_chan()
566 		rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300202);  in r12a_set_chan()
569 		rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);  in r12a_set_chan()
583 		if (rtwn_read_1(sc, 0x837) & 0x04)  in r12a_set_chan()
584 			val = 0x01400000;  in r12a_set_chan()
586 			val = 0x01800000;  in r12a_set_chan()
588 			val = 0x01c00000;  in r12a_set_chan()
590 		rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);  in r12a_set_chan()
592 		val = 0x0;  in r12a_set_chan()
603 		rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);  in r12a_set_chan()
606 		rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);  in r12a_set_chan()
607 		rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);  in r12a_set_chan()
618 		if (rtwn_read_1(sc, 0x837) & 0x04)  in r12a_set_chan()
619 			val = 0x01800000;  in r12a_set_chan()
621 			val = 0x01c00000;  in r12a_set_chan()
623 			val = 0x02000000;  in r12a_set_chan()
625 		rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);  in r12a_set_chan()
628 			rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);  in r12a_set_chan()
630 			rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);  in r12a_set_chan()
632 		val = 0x400;  in r12a_set_chan()
634 		rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);  in r12a_set_chan()
637 		rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);  in r12a_set_chan()
638 		rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);  in r12a_set_chan()
641 			val = 0x01c00000;  in r12a_set_chan()
643 			val = 0x02000000;  in r12a_set_chan()
645 		rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);  in r12a_set_chan()
647 		val = 0xc00;  in r12a_set_chan()
653 	for (i = 0; i < sc->nrxchains; i++)  in r12a_set_chan()
654 		rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val);  in r12a_set_chan()
667 	    0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM);  in r12a_set_band_2ghz()
669 	rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);  in r12a_set_band_2ghz()
670 	rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);  in r12a_set_band_2ghz()
673 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);  in r12a_set_band_2ghz()
676 	case 0:  in r12a_set_band_2ghz()
679 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);  in r12a_set_band_2ghz()
680 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);  in r12a_set_band_2ghz()
681 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);  in r12a_set_band_2ghz()
682 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);  in r12a_set_band_2ghz()
685 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);  in r12a_set_band_2ghz()
686 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);  in r12a_set_band_2ghz()
687 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);  in r12a_set_band_2ghz()
688 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);  in r12a_set_band_2ghz()
689 		rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);  in r12a_set_band_2ghz()
692 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);  in r12a_set_band_2ghz()
693 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);  in r12a_set_band_2ghz()
694 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);  in r12a_set_band_2ghz()
695 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);  in r12a_set_band_2ghz()
698 		rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77);  in r12a_set_band_2ghz()
699 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);  in r12a_set_band_2ghz()
700 		rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);  in r12a_set_band_2ghz()
701 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);  in r12a_set_band_2ghz()
707 	rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);  in r12a_set_band_2ghz()
708 	rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);  in r12a_set_band_2ghz()
713 	rtwn_write_1(sc, R12A_CCK_CHECK, 0);  in r12a_set_band_2ghz()
724 	for (ntries = 0; ntries < 100; ntries++) {  in r12a_set_band_5ghz()
725 		if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)  in r12a_set_band_5ghz()
740 	rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);  in r12a_set_band_5ghz()
741 	rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);  in r12a_set_band_5ghz()
744 	rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);  in r12a_set_band_5ghz()
747 	case 0:  in r12a_set_band_5ghz()
748 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);  in r12a_set_band_5ghz()
749 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);  in r12a_set_band_5ghz()
750 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
751 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
754 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);  in r12a_set_band_5ghz()
755 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);  in r12a_set_band_5ghz()
756 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);  in r12a_set_band_5ghz()
757 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);  in r12a_set_band_5ghz()
761 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);  in r12a_set_band_5ghz()
762 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);  in r12a_set_band_5ghz()
763 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
764 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
767 		rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);  in r12a_set_band_5ghz()
768 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);  in r12a_set_band_5ghz()
769 		rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
770 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
771 		rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);  in r12a_set_band_5ghz()
774 		rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33);  in r12a_set_band_5ghz()
775 		rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);  in r12a_set_band_5ghz()
776 		rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);  in r12a_set_band_5ghz()
777 		rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);  in r12a_set_band_5ghz()
783 	rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);  in r12a_set_band_5ghz()
784 	rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);  in r12a_set_band_5ghz()