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/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9002phy.h30 #define AR_PHY_TX_PWRCTRL4 0xa264
31 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
32 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
33 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
36 #define AR_PHY_TX_PWRCTRL6_0 0xa270
37 #define AR_PHY_TX_PWRCTRL6_1 0xb270
38 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
41 #define AR_PHY_TX_PWRCTRL7 0xa274
42 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
45 #define AR_PHY_TX_PWRCTRL8 0xa278
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie.txt22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
70 reg = <0x01ffc000 0x04000>,
71 <0x01f00000 0x80000>;
76 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
77 0x81000000 0 0 0x01f80000 0 0x00010000
78 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
83 interrupt-map-mask = <0 0 0 0x7>;
84 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
85 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfsl,imx6q-pcie.yaml167 reg = <0x01ffc000 0x04000>,
168 <0x01f00000 0x80000>;
173 bus-range = <0x00 0xff>;
174 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
175 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsadefs.h43 #define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error …
55 #define MPI_QUEUE_NORMAL 0
65 #define DIR_NODATA 0x000
66 #define DIR_READ 0x100
67 #define DIR_WRITE 0x200
70 #define TLR_MASK 0x00000003
74 #define PORTID_MASK 0x0000000F
75 #define PORTID_V_MASK 0x000000FF
76 #define PHYID_MASK 0x0000000F
77 #define PHYID_V_MASK 0x000000FF
[all …]
H A Dspcdefs.h42 #define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */
43 #define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */
44 #define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */
45 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */
46 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */
47 #define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */
64 bit32 Header; /* Bits [11:0] - Message operation code */
75 #define V_BIT 0x1
77 #define V_MASK 0x1
78 #define BC_MASK 0x1F
[all …]
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini-dlink-dir-685.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
61 #size-cells = <0>;
70 panel: display@0 {
72 reg = <0>;
130 gpio-fan,speed-map = <0 0>, <10000 1>;
178 #size-cells = <0>;
182 reg = <0x26>;
203 #address-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
[all...]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300desc.h94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal.h43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
57 #define HAL_WLAON_REG_BASE 0x01f80000
60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
[all …]
/freebsd/secure/lib/libcrypt/
H A Dcrypt-des.c108 14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7,
109 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8,
110 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0,
111 15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13
114 15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10,
115 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5,
116 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15,
117 13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9
120 10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8,
121 13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all...]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_type.h82 #define IXGBE_INTEL_VENDOR_ID 0x8086
85 #define IXGBE_DEV_ID_82598 0x10B6
86 #define IXGBE_DEV_ID_82598_BX 0x1508
87 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
88 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
89 #define IXGBE_DEV_ID_82598AT 0x10C8
90 #define IXGBE_DEV_ID_82598AT2 0x150B
91 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
92 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
93 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]