Lines Matching +full:0 +full:x01f80000
43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
57 #define HAL_WLAON_REG_BASE 0x01f80000
60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
107 #define HAL_TCL2_RING_HP 0x00002008
108 #define HAL_TCL_RING_HP 0x00002018
116 #define HAL_TCL_STATUS_RING_HP 0x00002030
119 #define HAL_REO1_GEN_ENABLE 0x00000000
120 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004
121 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
122 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
123 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
198 #define HAL_CE_DST_RING_BASE_LSB 0x00000000
199 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058
200 #define HAL_CE_DST_RING_CTRL 0x000000b0
203 #define HAL_CE_DST_RING_HP 0x00000400
204 #define HAL_CE_DST_STATUS_RING_HP 0x00000408
216 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048
217 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c
218 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058
219 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c
220 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
221 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
222 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
224 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084
227 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0
234 #define HAL_WBM_RELEASE_RING_HP 0x00003018
243 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0
244 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8
248 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
249 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
256 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
257 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
259 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
273 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
275 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
281 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
283 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
290 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
292 #define HAL_ADDR_LSB_REG_MASK 0xffffffff
300 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
306 #define BASE_ADDR_MATCH_TAG_VAL 0x5
308 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff
309 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff
310 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff
311 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff
312 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
313 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff
314 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff
315 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
316 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff
317 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff
318 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
319 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff
320 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff
321 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
322 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
325 #define HAL_IPQ5018_CE_WFSS_REG_BASE 0x08400000
326 #define HAL_IPQ5018_CE_SIZE 0x200000
333 HAL_SRNG_RING_ID_REO2SW1 = 0,
415 #define HAL_SRNG_REG_GRP_R0 0
467 HAL_REO_CMD_GET_QUEUE_STATS = 0,
486 HAL_REO_CMD_SUCCESS = 0,
490 HAL_REO_CMD_DRAIN = 0xff,
519 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
520 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
521 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
522 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
523 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
524 #define HAL_SRNG_FLAGS_CACHED 0x20000000
525 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
526 #define HAL_SRNG_FLAGS_REMAP_CE_RING 0x10000000
690 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000
692 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
781 #define HAL_HASH_ROUTING_RING_TCL 0
802 u32 rx_bitmap[8]; /* Bitmap from 0-255 */