Lines Matching +full:0 +full:x01f80000
42 #define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */
43 #define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */
44 #define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */
45 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */
46 #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */
47 #define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */
64 bit32 Header; /* Bits [11:0] - Message operation code */
75 #define V_BIT 0x1
77 #define V_MASK 0x1
78 #define BC_MASK 0x1F
79 #define OBID_MASK 0x3F
80 #define CAT_MASK 0x0F
81 #define OPCODE_MASK 0xFFF
82 #define HEADER_V_MASK 0x80000000
83 #define HEADER_BC_MASK 0x1f000000
113 /* bit23-0 inbound queue table offset */
116 /* bit23-0 outbound queue table offset */
123 …bit32 outboundHWEventPID0_3; /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserv…
124 /* bit0-7 outbound queue number of SAS_HW event for PhyId 0 */
133 …bit32 outboundNCQEventPID0_3; /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reser…
134 /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 0 */
143 …bit32 outboundTargetITNexusEventPID0_3; /**< DWE outbound target ITNexus Event for PortId 0 to 3,…
144 /* bit0-7 outbound queue number of ITNexus event for PhyId 0 */
153 …bit32 outboundTargetSSPEventPID0_3; /**< DW10 outbound target SSP event for PordId 0 to 3, SP…
154 /* bit0-7 outbound queue number of SSP event for PhyId 0 */
163 bit32 ioAbortDelay; /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/
167 bit32 eventLogSize; /**< DW16 Size of MSGU Event log, 0 means log disable */
169 /* bit3-0 log severity, 0x0 Disable Logging */
170 /* 0x1 Critical Error */
171 /* 0x2 Minor Error */
172 /* 0x3 Warning */
173 /* 0x4 Information */
174 /* 0x5 Debugging */
175 /* 0x6 - 0xF Reserved */
178 bit32 IOPeventLogSize; /**< DW1A Size of IOP Event log, 0 means log disable */
180 /* bit3-0 log severity, 0x0 Critical Error */
181 /* 0x1 Minor Error */
182 /* 0x2 Warning */
183 /* 0x3 Information */
184 /* 0x4 Unknown */
185 /* 0x5 - 0xF Reserved */
196 /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */
203 /* bit23-0 phy calib table offset */
206 /* bit23-0 interrupt vector table offset */
209 /* bit23-0 phy attribute table offset */
211 …bit32 portRecoveryResetTimer; /* Offset 0x25 [31:16] Port recovery timer default that i…
214 … [15:0] Port reset timer default that is used 3 (i.e 300ms) for all
217 …bit32 interruptReassertionDelay; /* Offset 0x26 [23:0] Remind host of outbound completion …
219 bit32 ilaRevision; /* Offset 0x27 */
223 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 (R) */
224 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 (R) */
225 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 (R) */
226 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 (R) */
227 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 (R) */
228 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 (R) */
229 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 (R) */
230 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 (R) */
231 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 (R) */
232 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 (W) */
233 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28 /* DWORD 0x0A (W) */ /* reserved for SPCV */
234 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C /* DWORD 0x0B (W) */ /* reserved for SPCV */
235 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30 /* DWORD 0x0C (W) */ /* reserved for SPCV */
236 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34 /* DWORD 0x0D (W) */ /* reserved for SPCV */
237 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38 /* DWORD 0x0E (W) */ /* reserved for SPCV */
238 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C /* DWORD 0x0F (W) */ /* reserved for SPCV */
239 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40 /* DWORD 0x10 (W) */ /* reserved for SPCV */
240 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44 /* DWORD 0x11 (W) */ /* reserved for SPCV */
241 #define MAIN_IO_ABORT_DELAY 0x48 /* DWORD 0x12 (W) */ /* reserved for SPCV */
242 #define MAIN_CUSTOMER_SETTING 0x4C /* DWORD 0x13 (W) */ /* reserved for SPCV */
243 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 (W) */
244 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 (W) */
245 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 (W) */
246 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 (W) */
247 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 (W) */
248 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 (W) */
249 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A (W) */
250 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B (W) */
251 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C (W) */
252 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D (R) */
253 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E (R) */
254 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F (R) */
255 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 (R) */
256 #define MAIN_HDA_FLAGS_OFFSET 0x84 /* DWORD 0x21 (R) */ /* reserved for SPCV */
257 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 (R) */
258 #define MAIN_INT_VEC_TABLE_OFFSET 0x8C /* DWORD 0x23 (W) */ /* for SPCV */
259 #define MAIN_PHY_ATTRIBUTE_OFFSET 0x90 /* DWORD 0x24 (W) */ /* for SPCV */
260 #define MAIN_PRECTD_PRESETD 0x94 /* DWORD 0x25 (W) */ /* for SPCV */
261 #define MAIN_IRAD_RESERVED 0x98 /* DWORD 0x26 (W) */ /* for SPCV */
262 #define MAIN_MOQFOT_MOQFOES 0x9C /* DWORD 0x27 (W) */ /* for SPCV */
263 #define MAIN_MERRDCTO_MERRDCES 0xA0 /* DWORD 0x28 (W) */ /* for SPCV */
264 #define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN 0xA4 /* DWORD 0x29 (W) */ /* for SPCV */
265 #define MAIN_INACTIVE_ILA_REVSION 0xA8 /* DWORD 0x2A (W) */ /* for SPCV V 3.02 */
266 #define MAIN_SEEPROM_REVSION 0xAC /* DWORD 0x2B (W) */ /* for SPCV V 3.02 */
267 #define MAIN_UNKNOWN1 0xB0 /* DWORD 0x2C (W) */ /* for SPCV V 3.03 */
268 #define MAIN_UNKNOWN2 0xB4 /* DWORD 0x2D (W) */ /* for SPCV V 3.03 */
269 #define MAIN_UNKNOWN3 0xB8 /* DWORD 0x2E (W) */ /* for SPCV V 3.03 */
270 #define MAIN_XCBI_REF_TAG_PAT 0xBC /* DWORD 0x2F (W) */ /* for SPCV V 3.03 */
271 #define MAIN_AWT_MIDRANGE 0xC0 /* DWORD 0x30 (W) */ /* for SPCV V 3.03 */
279 #define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000
282 #define MAIN_MAX_IB_MASK 0x000000ff /* bit7-0 */
283 #define MAIN_MAX_OB_MASK 0x0000ff00 /* bit15-8 */
284 #define MAIN_PHY_COUNT_MASK 0x01f80000 /* bit24-19 */
285 #define MAIN_QSUPPORT_BITS 0x0007ffff
286 #define MAIN_SAS_SUPPORT_BITS 0xfe000000
289 #define MAIN_MAX_SGL_BITS 0xFFFF
290 #define MAIN_MAX_DEV_BITS 0xFFFF0000
293 #define MAIN_HDA_FLAG_BITS 0x000000FF
295 #define FATAL_ERROR_INT_BITS 0xFF
296 #define INT_REASRT_ENABLE 0x00020000
297 #define INT_REASRT_MS_ENABLE 0x00040000
298 #define INT_REASRT_DELAY_BITS 0xFFF80000
305 #define IB_PROPERITY_OFFSET 0x00
306 #define IB_BASE_ADDR_HI_OFFSET 0x04
307 #define IB_BASE_ADDR_LO_OFFSET 0x08
308 #define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
309 #define IB_CI_BASE_ADDR_LO_OFFSET 0x10
310 #define IB_PIPCI_BAR 0x14
311 #define IB_PIPCI_BAR_OFFSET 0x18
312 #define IB_RESERVED_OFFSET 0x1C
315 #define OB_PROPERITY_OFFSET 0x00
316 #define OB_BASE_ADDR_HI_OFFSET 0x04
317 #define OB_BASE_ADDR_LO_OFFSET 0x08
318 #define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
319 #define OB_PI_BASE_ADDR_LO_OFFSET 0x10
320 #define OB_CIPCI_BAR 0x14
321 #define OB_CIPCI_BAR_OFFSET 0x18
322 #define OB_INTERRUPT_COALES_OFFSET 0x1C
323 #define OB_DYNAMIC_COALES_OFFSET 0x20
325 #define OB_PROPERTY_INT_ENABLE 0x40000000
328 #define GST_GSTLEN_MPIS_OFFSET 0x00
329 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
330 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
331 #define GST_MSGUTCNT_OFFSET 0x0C
332 #define GST_IOPTCNT_OFFSET 0x10
333 #define GST_IOP1TCNT_OFFSET 0x14
334 #define GST_PHYSTATE_OFFSET 0x18 /* SPCV reserved */
335 #define GST_PHYSTATE0_OFFSET 0x18 /* SPCV reserved */
336 #define GST_PHYSTATE1_OFFSET 0x1C /* SPCV reserved */
337 #define GST_PHYSTATE2_OFFSET 0x20 /* SPCV reserved */
338 #define GST_PHYSTATE3_OFFSET 0x24 /* SPCV reserved */
339 #define GST_PHYSTATE4_OFFSET 0x28 /* SPCV reserved */
340 #define GST_PHYSTATE5_OFFSET 0x2C /* SPCV reserved */
341 #define GST_PHYSTATE6_OFFSET 0x30 /* SPCV reserved */
342 #define GST_PHYSTATE7_OFFSET 0x34 /* SPCV reserved */
343 #define GST_GPIO_PINS_OFFSET 0x38
344 #define GST_RERRINFO_OFFSET 0x44
347 #define GST_MPI_STATE_UNINIT 0x00
348 #define GST_MPI_STATE_INIT 0x01
349 #define GST_MPI_STATE_TERMINATION 0x02
350 #define GST_MPI_STATE_ERROR 0x03
351 #define GST_MPI_STATE_MASK 0x07
353 #define GST_INF_STATE_BITS 0xfffe0007
357 #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
358 #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */
361 #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
362 #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
363 #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
364 #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
365 #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
366 #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
368 #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
369 #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
371 #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
372 #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
373 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
374 #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
376 #define IOCTL_ERROR_NO_FATAL_ERROR 0x77
400 … /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */
401 /**< bit00 Phy Start state n, 0 not started, 1 started */
402 /**< bit01 Phy Link state n, 0 link down, 1 link up */
446 /**< When set to 0, this queue is disabled */
471 /**< When set to 0, this queue is disabled */
484 /**< If set to 0, interrupts for this queue are disable */
507 #define INT_VT_Coal_CNT_TO 0
522 #define PHY_STATE 0